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a8aaad127d
When we are scheduling the load and addi, if all other heuristic didn't take effect, we will try to schedule the addi before the load, to hide the latency, and avoid the true dependency added by RA. And this only take effects for Power9. Differential Revision: https://reviews.llvm.org/D61930 llvm-svn: 361600
124 lines
4.4 KiB
YAML
124 lines
4.4 KiB
YAML
# RUN: llc -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu -start-before machine-scheduler -stop-after machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu -disable-ppc-sched-addi-load -start-before machine-scheduler -stop-after machine-scheduler \
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# RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-DISABLE %s
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# RUN: llc -mcpu=pwr8 -mtriple powerpc64le-unknown-linux-gnu -start-before machine-scheduler -stop-after machine-scheduler -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-P8 %s
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# Test that if the scheduler moves the addi before the load.
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--- |
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target datalayout = "e-m:e-i64:64-n32:64"
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define i64 @foo(i8* %p, i8* %q) {
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entry:
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br label %while.cond6.i
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while.cond6.i:
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%n.0 = phi i64 [ 0, %entry ], [ %n.1, %while.cond6.i ]
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%conv = and i64 %n.0, 4294967295
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%arrayidx = getelementptr inbounds i8, i8* %p, i64 %conv
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%0 = load i8, i8* %arrayidx, align 1
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%arrayidx4 = getelementptr inbounds i8, i8* %q, i64 %conv
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%1 = load i8, i8* %arrayidx4, align 1
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%cmp = icmp eq i8 %0, %1
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%n.1 = add i64 %conv, 1
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br i1 %cmp, label %while.cond6.i, label %while.end
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while.end:
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ret i64 %n.0
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}
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...
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---
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name: foo
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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- { id: 5, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: gprc, preferred-register: '' }
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- { id: 8, class: crrc, preferred-register: '' }
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- { id: 9, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%2' }
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- { reg: '$x4', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $x3, $x4
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%3:g8rc_and_g8rc_nox0 = COPY $x4
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%2:g8rc_and_g8rc_nox0 = COPY $x3
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%9:g8rc = LI8 0
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bb.1.while.cond6.i:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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%0:g8rc = COPY %9
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%5:g8rc_and_g8rc_nox0 = RLDICL %0, 0, 32
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%6:gprc = LBZX %2, %5 :: (load 1 from %ir.arrayidx)
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%7:gprc = LBZX %3, %5 :: (load 1 from %ir.arrayidx4)
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%9:g8rc = ADDI8 %5, 1
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%8:crrc = CMPLW %6, %7
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BCC 76, %8, %bb.1
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B %bb.2
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; CHECK-LABEL: foo
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; CHECK: %5:g8rc_and_g8rc_nox0 = RLDICL %0, 0, 32
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; CHECK-NEXT: %9:g8rc = ADDI8 %5, 1
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; CHECK-NEXT: %6:gprc = LBZX %2, %5 :: (load 1 from %ir.arrayidx)
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; CHECK-NEXT: %7:gprc = LBZX %3, %5 :: (load 1 from %ir.arrayidx4)
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; CHECK-NEXT: %8:crrc = CMPLW %6, %7
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; CHECK-NEXT: BCC 76, %8
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; CHECK-DISABLE-LABEL: foo
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; CHECK-DISABLE: %5:g8rc_and_g8rc_nox0 = RLDICL %0, 0, 32
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; CHECK-DISABLE-NEXT: %6:gprc = LBZX %2, %5 :: (load 1 from %ir.arrayidx)
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; CHECK-DISABLE-NEXT: %7:gprc = LBZX %3, %5 :: (load 1 from %ir.arrayidx4)
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; CHECK-DISABLE-NEXT: %9:g8rc = ADDI8 %5, 1
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; CHECK-DISABLE-NEXT: %8:crrc = CMPLW %6, %7
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; CHECK-DISABLE-NEXT: BCC 76, %8
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; CHECK-P8-LABEL: foo
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; CHECK-P8: %5:g8rc_and_g8rc_nox0 = RLDICL %0, 0, 32
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; CHECK-P8-NEXT: %6:gprc = LBZX %2, %5 :: (load 1 from %ir.arrayidx)
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; CHECK-P8-NEXT: %7:gprc = LBZX %3, %5 :: (load 1 from %ir.arrayidx4)
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; CHECK-P8-NEXT: %8:crrc = CMPLW %6, %7
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; CHECK-P8-NEXT: %9:g8rc = ADDI8 %5, 1
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; CHECK-P8-NEXT: BCC 76, %8
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bb.2.while.end:
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$x3 = COPY %0
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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