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2f3956c41c
When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
126 lines
3.8 KiB
LLVM
126 lines
3.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck --check-prefix=CHECK-P9-VECTOR %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd
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define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
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; CHECK-LABEL: testi0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: lfdx f1, 0, r4
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: xxspltd vs1, vs1, 0
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; CHECK-NEXT: xxpermdi v2, vs0, vs1, 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-VECTOR-LABEL: testi0:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-VECTOR-NEXT: lfdx f1, 0, r4
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; CHECK-P9-VECTOR-NEXT: xxspltd vs1, vs1, 0
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; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-VECTOR-NEXT: xxpermdi v2, vs0, vs1, 1
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; CHECK-P9-VECTOR-NEXT: blr
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;
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; CHECK-P9-LABEL: testi0:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lfd [[REG:f[0-9]+]], 0(r4)
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; CHECK-P9-NEXT: lxv [[REG1:vs[0-9]+]], 0(r3)
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; CHECK-P9-NEXT: xxpermdi [[REG2:vs[0-9]+]], [[REG]], [[REG]], 2
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; CHECK-P9-NEXT: xxpermdi v2, [[REG1]], [[REG2]], 1
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%s = load double, double* %p2
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%r = insertelement <2 x double> %v, double %s, i32 0
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ret <2 x double> %r
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}
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define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
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; CHECK-LABEL: testi1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: lfdx f1, 0, r4
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: xxspltd vs1, vs1, 0
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; CHECK-NEXT: xxmrgld v2, vs1, vs0
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; CHECK-NEXT: blr
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;
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; CHECK-P9-VECTOR-LABEL: testi1:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-VECTOR-NEXT: lfdx f1, 0, r4
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; CHECK-P9-VECTOR-NEXT: xxspltd vs1, vs1, 0
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; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-VECTOR-NEXT: xxmrgld v2, vs1, vs0
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; CHECK-P9-VECTOR-NEXT: blr
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;
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; CHECK-P9-LABEL: testi1:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lfd [[REG:f[0-9]+]], 0(r4)
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; CHECK-P9-NEXT: lxv [[REG1:vs[0-9]+]], 0(r3)
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; CHECK-P9-NEXT: xxpermdi [[REG2:vs[0-9]+]], [[REG]], [[REG]], 2
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; CHECK-P9-NEXT: xxmrgld v2, [[REG2]], [[REG1]]
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%s = load double, double* %p2
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%r = insertelement <2 x double> %v, double %s, i32 1
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ret <2 x double> %r
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}
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define double @teste0(<2 x double>* %p1) {
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; CHECK-LABEL: teste0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lxvd2x vs1, 0, r3
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; CHECK: blr
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;
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; CHECK-P9-VECTOR-LABEL: teste0:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lxvd2x vs1, 0, r3
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; CHECK-P9-VECTOR: blr
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;
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; CHECK-P9-LABEL: teste0:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lfd f1, 0(r3)
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%r = extractelement <2 x double> %v, i32 0
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ret double %r
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}
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define double @teste1(<2 x double>* %p1) {
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; CHECK-LABEL: teste1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: xxswapd vs1, vs0
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; CHECK: blr
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;
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; CHECK-P9-VECTOR-LABEL: teste1:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-VECTOR-NEXT: xxswapd vs1, vs0
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; CHECK-P9-VECTOR: blr
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;
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; CHECK-P9-LABEL: teste1:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lfd f1, 8(r3)
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%r = extractelement <2 x double> %v, i32 1
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ret double %r
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}
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