mirror of
https://github.com/RPCS3/llvm-mirror.git
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0e5671c4ab
llvm-svn: 267128
485 lines
18 KiB
C++
485 lines
18 KiB
C++
//===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the RegisterBankInfo class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm> // For std::max.
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#define DEBUG_TYPE "registerbankinfo"
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using namespace llvm;
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const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
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const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
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/// Get the size in bits of the \p Reg.
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///
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/// \pre \p Reg != 0 (NoRegister).
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static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) {
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const TargetRegisterClass *RC = nullptr;
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// The size is not directly available for physical registers.
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// Instead, we need to access a register class that contains Reg and
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// get the size of that register class.
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RC = TRI.getMinimalPhysRegClass(Reg);
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} else {
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unsigned RegSize = MRI.getSize(Reg);
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// If Reg is not a generic register, query the register class to
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// get its size.
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if (RegSize)
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return RegSize;
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// Since Reg is not a generic register, it must have a register class.
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RC = MRI.getRegClass(Reg);
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}
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assert(RC && "Unable to deduce the register class");
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return RC->getSize() * 8;
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}
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//------------------------------------------------------------------------------
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// RegisterBankInfo implementation.
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//------------------------------------------------------------------------------
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RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
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: NumRegBanks(NumRegBanks) {
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RegBanks.reset(new RegisterBank[NumRegBanks]);
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}
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bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
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DEBUG(for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
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const RegisterBank &RegBank = getRegBank(Idx);
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assert(Idx == RegBank.getID() &&
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"ID does not match the index in the array");
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dbgs() << "Verify " << RegBank << '\n';
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assert(RegBank.verify(TRI) && "RegBank is invalid");
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});
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return true;
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}
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void RegisterBankInfo::createRegisterBank(unsigned ID, const char *Name) {
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DEBUG(dbgs() << "Create register bank: " << ID << " with name \"" << Name
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<< "\"\n");
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RegisterBank &RegBank = getRegBank(ID);
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assert(RegBank.getID() == RegisterBank::InvalidID &&
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"A register bank should be created only once");
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RegBank.ID = ID;
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RegBank.Name = Name;
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}
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void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
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const TargetRegisterInfo &TRI,
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bool AddTypeMapping) {
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RegisterBank &RB = getRegBank(ID);
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unsigned NbOfRegClasses = TRI.getNumRegClasses();
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DEBUG(dbgs() << "Add coverage for: " << RB << '\n');
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// Check if RB is underconstruction.
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if (!RB.isValid())
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RB.ContainedRegClasses.resize(NbOfRegClasses);
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else if (RB.covers(*TRI.getRegClass(RCId)))
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// If RB already covers this register class, there is nothing
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// to do.
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return;
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BitVector &Covered = RB.ContainedRegClasses;
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SmallVector<unsigned, 8> WorkList;
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WorkList.push_back(RCId);
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Covered.set(RCId);
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unsigned &MaxSize = RB.Size;
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do {
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unsigned RCId = WorkList.pop_back_val();
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const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId);
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DEBUG(dbgs() << "Examine: " << TRI.getRegClassName(&CurRC)
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<< "(Size*8: " << (CurRC.getSize() * 8) << ")\n");
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// Remember the biggest size in bits.
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MaxSize = std::max(MaxSize, CurRC.getSize() * 8);
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// If we have been asked to record the type supported by this
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// register bank, do it now.
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if (AddTypeMapping)
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for (MVT::SimpleValueType SVT :
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make_range(CurRC.vt_begin(), CurRC.vt_end()))
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recordRegBankForType(getRegBank(ID), SVT);
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// Walk through all sub register classes and push them into the worklist.
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bool First = true;
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for (BitMaskClassIterator It(CurRC.getSubClassMask(), TRI); It.isValid();
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++It) {
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unsigned SubRCId = It.getID();
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if (!Covered.test(SubRCId)) {
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if (First)
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DEBUG(dbgs() << " Enqueue sub-class: ");
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DEBUG(dbgs() << TRI.getRegClassName(TRI.getRegClass(SubRCId)) << ", ");
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WorkList.push_back(SubRCId);
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// Remember that we saw the sub class.
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Covered.set(SubRCId);
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First = false;
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}
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}
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if (!First)
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DEBUG(dbgs() << '\n');
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// Push also all the register classes that can be accessed via a
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// subreg index, i.e., its subreg-class (which is different than
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// its subclass).
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//
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// Note: It would probably be faster to go the other way around
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// and have this method add only super classes, since this
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// information is available in a more efficient way. However, it
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// feels less natural for the client of this APIs plus we will
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// TableGen the whole bitset at some point, so compile time for
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// the initialization is not very important.
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First = true;
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for (unsigned SubRCId = 0; SubRCId < NbOfRegClasses; ++SubRCId) {
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if (Covered.test(SubRCId))
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continue;
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bool Pushed = false;
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const TargetRegisterClass *SubRC = TRI.getRegClass(SubRCId);
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for (SuperRegClassIterator SuperRCIt(SubRC, &TRI); SuperRCIt.isValid();
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++SuperRCIt) {
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if (Pushed)
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break;
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for (BitMaskClassIterator It(SuperRCIt.getMask(), TRI); It.isValid();
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++It) {
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unsigned SuperRCId = It.getID();
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if (SuperRCId == RCId) {
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if (First)
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DEBUG(dbgs() << " Enqueue subreg-class: ");
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DEBUG(dbgs() << TRI.getRegClassName(SubRC) << ", ");
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WorkList.push_back(SubRCId);
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// Remember that we saw the sub class.
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Covered.set(SubRCId);
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Pushed = true;
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First = false;
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break;
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}
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}
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}
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}
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if (!First)
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DEBUG(dbgs() << '\n');
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} while (!WorkList.empty());
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}
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const RegisterBank *
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RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const {
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg));
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assert(Reg && "NoRegister does not have a register bank");
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const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
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if (RegClassOrBank.is<const RegisterBank *>())
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return RegClassOrBank.get<const RegisterBank *>();
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const TargetRegisterClass *RC =
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RegClassOrBank.get<const TargetRegisterClass *>();
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if (RC)
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return &getRegBankFromRegClass(*RC);
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return nullptr;
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}
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const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
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const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI) const {
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// The mapping of the registers may be available via the
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// register class constraints.
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const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
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if (!RC)
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return nullptr;
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const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
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// Sanity check that the target properly implemented getRegBankFromRegClass.
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assert(RegBank.covers(*RC) &&
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"The mapping of the register bank does not make sense");
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return &RegBank;
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}
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RegisterBankInfo::InstructionMapping
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RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
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RegisterBankInfo::InstructionMapping Mapping(DefaultMappingID, /*Cost*/ 1,
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MI.getNumOperands());
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const MachineFunction &MF = *MI.getParent()->getParent();
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const TargetSubtargetInfo &STI = MF.getSubtarget();
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const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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// We may need to query the instruction encoding to guess the mapping.
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const TargetInstrInfo &TII = *STI.getInstrInfo();
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// Before doing anything complicated check if the mapping is not
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// directly available.
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bool CompleteMapping = true;
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// For copies we want to walk over the operands and try to find one
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// that has a register bank.
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bool isCopyLike = MI.isCopy() || MI.isPHI();
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// Remember the register bank for reuse for copy-like instructions.
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const RegisterBank *RegBank = nullptr;
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// Remember the size of the register for reuse for copy-like instructions.
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unsigned RegSize = 0;
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for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
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const MachineOperand &MO = MI.getOperand(OpIdx);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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// The register bank of Reg is just a side effect of the current
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// excution and in particular, there is no reason to believe this
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// is the best default mapping for the current instruction. Keep
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// it as an alternative register bank if we cannot figure out
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// something.
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const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
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// For copy-like instruction, we want to reuse the register bank
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// that is already set on Reg, if any, since those instructions do
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// not have any constraints.
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const RegisterBank *CurRegBank = isCopyLike ? AltRegBank : nullptr;
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if (!CurRegBank) {
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// If this is a target specific instruction, we can deduce
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// the register bank from the encoding constraints.
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CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
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if (!CurRegBank) {
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// Check if we can deduce the register bank from the type of
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// the instruction.
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Type *MITy = MI.getType();
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if (MITy)
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CurRegBank = getRegBankForType(
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MVT::getVT(MITy, /*HandleUnknown*/ true).SimpleTy);
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if (!CurRegBank)
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// Use the current assigned register bank.
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// That may not make much sense though.
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CurRegBank = AltRegBank;
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if (!CurRegBank) {
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// All our attempts failed, give up.
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CompleteMapping = false;
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if (!isCopyLike)
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// MI does not carry enough information to guess the mapping.
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return InstructionMapping();
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// For copies, we want to keep interating to find a register
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// bank for the other operands if we did not find one yet.
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if (RegBank)
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break;
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continue;
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}
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}
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}
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RegBank = CurRegBank;
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RegSize = getSizeInBits(Reg, MRI, TRI);
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Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank);
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}
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if (CompleteMapping)
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return Mapping;
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assert(isCopyLike && "We should have bailed on non-copies at this point");
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// For copy like instruction, if none of the operand has a register
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// bank avialable, there is nothing we can propagate.
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if (!RegBank)
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return InstructionMapping();
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// This is a copy-like instruction.
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// Propagate RegBank to all operands that do not have a
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// mapping yet.
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for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
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const MachineOperand &MO = MI.getOperand(OpIdx);
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// Don't assign a mapping for non-reg operands.
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if (!MO.isReg())
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continue;
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// If a mapping already exists, do not touch it.
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if (!static_cast<const InstructionMapping *>(&Mapping)
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->getOperandMapping(OpIdx)
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.BreakDown.empty())
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continue;
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Mapping.setOperandMapping(OpIdx, RegSize, *RegBank);
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}
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return Mapping;
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}
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RegisterBankInfo::InstructionMapping
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RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
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if (Mapping.isValid())
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return Mapping;
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llvm_unreachable("The target must implement this");
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}
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RegisterBankInfo::InstructionMappings
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RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
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InstructionMappings PossibleMappings;
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// Put the default mapping first.
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PossibleMappings.push_back(getInstrMapping(MI));
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// Then the alternative mapping, if any.
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InstructionMappings AltMappings = getInstrAlternativeMappings(MI);
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for (InstructionMapping &AltMapping : AltMappings)
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PossibleMappings.emplace_back(std::move(AltMapping));
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#ifndef NDEBUG
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for (const InstructionMapping &Mapping : PossibleMappings)
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assert(Mapping.verify(MI) && "Mapping is invalid");
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#endif
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return PossibleMappings;
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}
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RegisterBankInfo::InstructionMappings
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RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
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// No alternative for MI.
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return InstructionMappings();
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}
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//------------------------------------------------------------------------------
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// Helper classes implementation.
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//------------------------------------------------------------------------------
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void RegisterBankInfo::PartialMapping::dump() const {
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print(dbgs());
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dbgs() << '\n';
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}
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bool RegisterBankInfo::PartialMapping::verify() const {
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assert(RegBank && "Register bank not set");
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assert(Length && "Empty mapping");
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assert((StartIdx < getHighBitIdx()) && "Overflow, switch to APInt?");
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// Check if the minimum width fits into RegBank.
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assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
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return true;
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}
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void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
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OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
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if (RegBank)
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OS << *RegBank;
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else
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OS << "nullptr";
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}
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bool RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
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assert(!BreakDown.empty() && "Value mapped nowhere?!");
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unsigned OrigValueBitWidth = 0;
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for (const RegisterBankInfo::PartialMapping &PartMap : BreakDown) {
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// Check that each register bank is big enough to hold the partial value:
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// this check is done by PartialMapping::verify
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assert(PartMap.verify() && "Partial mapping is invalid");
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// The original value should completely be mapped.
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// Thus the maximum accessed index + 1 is the size of the original value.
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OrigValueBitWidth =
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std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
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}
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assert(OrigValueBitWidth == ExpectedBitWidth && "BitWidth does not match");
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APInt ValueMask(OrigValueBitWidth, 0);
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for (const RegisterBankInfo::PartialMapping &PartMap : BreakDown) {
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// Check that the union of the partial mappings covers the whole value,
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// without overlaps.
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// The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
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APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
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PartMap.getHighBitIdx() + 1);
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ValueMask ^= PartMapMask;
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assert((ValueMask & PartMapMask) == PartMapMask &&
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"Some partial mappings overlap");
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}
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assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
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return true;
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}
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void RegisterBankInfo::ValueMapping::dump() const {
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print(dbgs());
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dbgs() << '\n';
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}
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void RegisterBankInfo::ValueMapping::print(raw_ostream &OS) const {
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OS << "#BreakDown: " << BreakDown.size() << " ";
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bool IsFirst = true;
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for (const PartialMapping &PartMap : BreakDown) {
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if (!IsFirst)
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OS << ", ";
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OS << '[' << PartMap << ']';
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IsFirst = false;
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}
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}
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void RegisterBankInfo::InstructionMapping::setOperandMapping(
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unsigned OpIdx, unsigned MaskSize, const RegisterBank &RegBank) {
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// Build the value mapping.
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assert(MaskSize <= RegBank.getSize() && "Register bank is too small");
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// Create the mapping object.
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getOperandMapping(OpIdx).BreakDown.push_back(
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PartialMapping(0, MaskSize, RegBank));
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}
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bool RegisterBankInfo::InstructionMapping::verify(
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const MachineInstr &MI) const {
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// Check that all the register operands are properly mapped.
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// Check the constructor invariant.
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assert(NumOperands == MI.getNumOperands() &&
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"NumOperands must match, see constructor");
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assert(MI.getParent() && MI.getParent()->getParent() &&
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"MI must be connected to a MachineFunction");
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const MachineFunction &MF = *MI.getParent()->getParent();
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(void)MF;
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for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
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const MachineOperand &MO = MI.getOperand(Idx);
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const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
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(void)MOMapping;
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if (!MO.isReg()) {
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assert(MOMapping.BreakDown.empty() &&
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"We should not care about non-reg mapping");
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continue;
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}
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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// Register size in bits.
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// This size must match what the mapping expects.
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assert(MOMapping.verify(getSizeInBits(
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Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
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"Value mapping is invalid");
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}
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return true;
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}
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void RegisterBankInfo::InstructionMapping::dump() const {
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print(dbgs());
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dbgs() << '\n';
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}
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void RegisterBankInfo::InstructionMapping::print(raw_ostream &OS) const {
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OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
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for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
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const ValueMapping &ValMapping = getOperandMapping(OpIdx);
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if (OpIdx)
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OS << ", ";
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OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
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}
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}
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