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328bb420a2
Summary: This always just used the same libcall as unordered, but the comparison predicate was different. This change appears to have been made when targets were given the ability to override the predicates. Before that they were hardcoded into the type legalizer. At that time we never inverted predicates and we handled ugt/ult/uge/ule compares by emitting an unordered check ORed with a ogt/olt/oge/ole checks. So only ordered needed an inverted predicate. Later ugt/ult/uge/ule were optimized to only call a single libcall and invert the compare. This patch removes the ordered entries and just uses the inverting logic that is now present. This removes some odd things in both the Mips and WebAssembly code. Reviewers: efriedma, ABataev, uweigand, cameron.mcinally, kpn Reviewed By: efriedma Subscribers: dschuff, sdardis, sbc100, arichardson, jgravelle-google, kristof.beyls, hiraditya, aheejin, sunfish, atanasyan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72536
788 lines
29 KiB
C++
788 lines
29 KiB
C++
//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips16.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16ISelLowering.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips16HardFloatInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-lower"
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static cl::opt<bool> DontExpandCondPseudos16(
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"mips16-dont-expand-cond-pseudo",
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cl::init(false),
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cl::desc("Don't expand conditional move related "
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"pseudos for Mips 16"),
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cl::Hidden);
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namespace {
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struct Mips16Libcall {
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RTLIB::Libcall Libcall;
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const char *Name;
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bool operator<(const Mips16Libcall &RHS) const {
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return std::strcmp(Name, RHS.Name) < 0;
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}
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};
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struct Mips16IntrinsicHelperType{
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const char* Name;
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const char* Helper;
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bool operator<(const Mips16IntrinsicHelperType &RHS) const {
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return std::strcmp(Name, RHS.Name) < 0;
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}
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bool operator==(const Mips16IntrinsicHelperType &RHS) const {
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return std::strcmp(Name, RHS.Name) == 0;
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}
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};
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}
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// Libcalls for which no helper is generated. Sorted by name for binary search.
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static const Mips16Libcall HardFloatLibCalls[] = {
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{ RTLIB::ADD_F64, "__mips16_adddf3" },
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{ RTLIB::ADD_F32, "__mips16_addsf3" },
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{ RTLIB::DIV_F64, "__mips16_divdf3" },
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{ RTLIB::DIV_F32, "__mips16_divsf3" },
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{ RTLIB::OEQ_F64, "__mips16_eqdf2" },
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{ RTLIB::OEQ_F32, "__mips16_eqsf2" },
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{ RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
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{ RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
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{ RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
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{ RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
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{ RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
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{ RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
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{ RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
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{ RTLIB::OGE_F64, "__mips16_gedf2" },
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{ RTLIB::OGE_F32, "__mips16_gesf2" },
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{ RTLIB::OGT_F64, "__mips16_gtdf2" },
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{ RTLIB::OGT_F32, "__mips16_gtsf2" },
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{ RTLIB::OLE_F64, "__mips16_ledf2" },
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{ RTLIB::OLE_F32, "__mips16_lesf2" },
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{ RTLIB::OLT_F64, "__mips16_ltdf2" },
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{ RTLIB::OLT_F32, "__mips16_ltsf2" },
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{ RTLIB::MUL_F64, "__mips16_muldf3" },
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{ RTLIB::MUL_F32, "__mips16_mulsf3" },
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{ RTLIB::UNE_F64, "__mips16_nedf2" },
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{ RTLIB::UNE_F32, "__mips16_nesf2" },
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{ RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
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{ RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
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{ RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
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{ RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
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{ RTLIB::SUB_F64, "__mips16_subdf3" },
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{ RTLIB::SUB_F32, "__mips16_subsf3" },
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{ RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
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{ RTLIB::UO_F64, "__mips16_unorddf2" },
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{ RTLIB::UO_F32, "__mips16_unordsf2" }
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};
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static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
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{"__fixunsdfsi", "__mips16_call_stub_2" },
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{"ceil", "__mips16_call_stub_df_2"},
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{"ceilf", "__mips16_call_stub_sf_1"},
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{"copysign", "__mips16_call_stub_df_10"},
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{"copysignf", "__mips16_call_stub_sf_5"},
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{"cos", "__mips16_call_stub_df_2"},
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{"cosf", "__mips16_call_stub_sf_1"},
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{"exp2", "__mips16_call_stub_df_2"},
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{"exp2f", "__mips16_call_stub_sf_1"},
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{"floor", "__mips16_call_stub_df_2"},
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{"floorf", "__mips16_call_stub_sf_1"},
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{"log2", "__mips16_call_stub_df_2"},
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{"log2f", "__mips16_call_stub_sf_1"},
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{"nearbyint", "__mips16_call_stub_df_2"},
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{"nearbyintf", "__mips16_call_stub_sf_1"},
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{"rint", "__mips16_call_stub_df_2"},
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{"rintf", "__mips16_call_stub_sf_1"},
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{"sin", "__mips16_call_stub_df_2"},
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{"sinf", "__mips16_call_stub_sf_1"},
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{"sqrt", "__mips16_call_stub_df_2"},
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{"sqrtf", "__mips16_call_stub_sf_1"},
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{"trunc", "__mips16_call_stub_df_2"},
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{"truncf", "__mips16_call_stub_sf_1"},
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};
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Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
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const MipsSubtarget &STI)
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: MipsTargetLowering(TM, STI) {
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// Set up the register classes
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addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
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if (!Subtarget.useSoftFloat())
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setMips16HardFloatLibCalls();
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i64, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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computeRegisterProperties(STI.getRegisterInfo());
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}
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const MipsTargetLowering *
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llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
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const MipsSubtarget &STI) {
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return new Mips16TargetLowering(TM, STI);
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}
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bool Mips16TargetLowering::allowsMisalignedMemoryAccesses(
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EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
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return false;
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}
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MachineBasicBlock *
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Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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switch (MI.getOpcode()) {
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default:
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return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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case Mips::SelBeqZ:
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return emitSel16(Mips::BeqzRxImm16, MI, BB);
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case Mips::SelBneZ:
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return emitSel16(Mips::BnezRxImm16, MI, BB);
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case Mips::SelTBteqZCmpi:
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return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
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case Mips::SelTBteqZSlti:
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return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
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case Mips::SelTBteqZSltiu:
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return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
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case Mips::SelTBtneZCmpi:
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return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
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case Mips::SelTBtneZSlti:
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return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
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case Mips::SelTBtneZSltiu:
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return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
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case Mips::SelTBteqZCmp:
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return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
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case Mips::SelTBteqZSlt:
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return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
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case Mips::SelTBteqZSltu:
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return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
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case Mips::SelTBtneZCmp:
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return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
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case Mips::SelTBtneZSlt:
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return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
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case Mips::SelTBtneZSltu:
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return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
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case Mips::BteqzT8CmpX16:
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return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
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case Mips::BteqzT8SltX16:
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return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
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case Mips::BteqzT8SltuX16:
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// TBD: figure out a way to get this or remove the instruction
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// altogether.
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return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
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case Mips::BtnezT8CmpX16:
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return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
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case Mips::BtnezT8SltX16:
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return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
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case Mips::BtnezT8SltuX16:
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// TBD: figure out a way to get this or remove the instruction
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// altogether.
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return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
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case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
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Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
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case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
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Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
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case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
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Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
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case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
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Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
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case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
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Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
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case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
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Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
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break;
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case Mips::SltCCRxRy16:
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return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
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break;
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case Mips::SltiCCRxImmX16:
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return emitFEXT_CCRXI16_ins
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(Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
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case Mips::SltiuCCRxImmX16:
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return emitFEXT_CCRXI16_ins
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(Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
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case Mips::SltuCCRxRy16:
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return emitFEXT_CCRX16_ins
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(Mips::SltuRxRy16, MI, BB);
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}
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}
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bool Mips16TargetLowering::isEligibleForTailCallOptimization(
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const CCState &CCInfo, unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const {
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// No tail call optimization for mips16.
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return false;
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}
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void Mips16TargetLowering::setMips16HardFloatLibCalls() {
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for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
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assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
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"Array not sorted!");
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if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
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setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
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}
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}
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//
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// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
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// cleaner way to do all of this but it will have to wait until the traditional
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// gcc mechanism is completed.
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//
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// For Pic, in order for Mips16 code to call Mips32 code which according the abi
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// have either arguments or returned values placed in floating point registers,
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// we use a set of helper functions. (This includes functions which return type
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// complex which on Mips are returned in a pair of floating point registers).
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//
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// This is an encoding that we inherited from gcc.
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// In Mips traditional O32, N32 ABI, floating point numbers are passed in
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// floating point argument registers 1,2 only when the first and optionally
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// the second arguments are float (sf) or double (df).
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// For Mips16 we are only concerned with the situations where floating point
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// arguments are being passed in floating point registers by the ABI, because
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// Mips16 mode code cannot execute floating point instructions to load those
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// values and hence helper functions are needed.
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// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
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// the helper function suffixs for these are:
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// 0, 1, 5, 9, 2, 6, 10
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// this suffix can then be calculated as follows:
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// for a given argument Arg:
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// Arg1x, Arg2x = 1 : Arg is sf
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// 2 : Arg is df
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// 0: Arg is neither sf or df
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// So this stub is the string for number Arg1x + Arg2x*4.
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// However not all numbers between 0 and 10 are possible, we check anyway and
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// assert if the impossible exists.
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//
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unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
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(ArgListTy &Args) const {
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unsigned int resultNum = 0;
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if (Args.size() >= 1) {
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Type *t = Args[0].Ty;
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if (t->isFloatTy()) {
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resultNum = 1;
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}
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else if (t->isDoubleTy()) {
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resultNum = 2;
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}
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}
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if (resultNum) {
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if (Args.size() >=2) {
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Type *t = Args[1].Ty;
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if (t->isFloatTy()) {
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resultNum += 4;
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}
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else if (t->isDoubleTy()) {
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resultNum += 8;
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}
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}
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}
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return resultNum;
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}
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//
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// Prefixes are attached to stub numbers depending on the return type.
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// return type: float sf_
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// double df_
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// single complex sc_
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// double complext dc_
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// others NO PREFIX
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//
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//
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// The full name of a helper function is__mips16_call_stub +
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// return type dependent prefix + stub number
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//
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// FIXME: This is something that probably should be in a different source file
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// and perhaps done differently but my main purpose is to not waste runtime
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// on something that we can enumerate in the source. Another possibility is
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// to have a python script to generate these mapping tables. This will do
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// for now. There are a whole series of helper function mapping arrays, one
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// for each return type class as outlined above. There there are 11 possible
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// entries. Ones with 0 are ones which should never be selected.
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//
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// All the arrays are similar except for ones which return neither
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// sf, df, sc, dc, in which we only care about ones which have sf or df as a
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// first parameter.
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//
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#define P_ "__mips16_call_stub_"
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#define MAX_STUB_NUMBER 10
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#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
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#define T P "0" , T1
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#define P P_
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static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
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{nullptr, T1 };
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#undef P
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#define P P_ "sf_"
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static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
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{ T };
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#undef P
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#define P P_ "df_"
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static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
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{ T };
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#undef P
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#define P P_ "sc_"
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static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
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{ T };
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#undef P
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#define P P_ "dc_"
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static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
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{ T };
|
|
#undef P
|
|
#undef P_
|
|
|
|
|
|
const char* Mips16TargetLowering::
|
|
getMips16HelperFunction
|
|
(Type* RetTy, ArgListTy &Args, bool &needHelper) const {
|
|
const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
|
|
#ifndef NDEBUG
|
|
const unsigned int maxStubNum = 10;
|
|
assert(stubNum <= maxStubNum);
|
|
const bool validStubNum[maxStubNum+1] =
|
|
{true, true, true, false, false, true, true, false, false, true, true};
|
|
assert(validStubNum[stubNum]);
|
|
#endif
|
|
const char *result;
|
|
if (RetTy->isFloatTy()) {
|
|
result = sfMips16Helper[stubNum];
|
|
}
|
|
else if (RetTy ->isDoubleTy()) {
|
|
result = dfMips16Helper[stubNum];
|
|
} else if (StructType *SRetTy = dyn_cast<StructType>(RetTy)) {
|
|
// check if it's complex
|
|
if (SRetTy->getNumElements() == 2) {
|
|
if ((SRetTy->getElementType(0)->isFloatTy()) &&
|
|
(SRetTy->getElementType(1)->isFloatTy())) {
|
|
result = scMips16Helper[stubNum];
|
|
} else if ((SRetTy->getElementType(0)->isDoubleTy()) &&
|
|
(SRetTy->getElementType(1)->isDoubleTy())) {
|
|
result = dcMips16Helper[stubNum];
|
|
} else {
|
|
llvm_unreachable("Uncovered condition");
|
|
}
|
|
} else {
|
|
llvm_unreachable("Uncovered condition");
|
|
}
|
|
} else {
|
|
if (stubNum == 0) {
|
|
needHelper = false;
|
|
return "";
|
|
}
|
|
result = vMips16Helper[stubNum];
|
|
}
|
|
needHelper = true;
|
|
return result;
|
|
}
|
|
|
|
void Mips16TargetLowering::
|
|
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
|
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
|
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
|
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
|
SDValue Chain) const {
|
|
SelectionDAG &DAG = CLI.DAG;
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
|
|
const char* Mips16HelperFunction = nullptr;
|
|
bool NeedMips16Helper = false;
|
|
|
|
if (Subtarget.inMips16HardFloat()) {
|
|
//
|
|
// currently we don't have symbols tagged with the mips16 or mips32
|
|
// qualifier so we will assume that we don't know what kind it is.
|
|
// and generate the helper
|
|
//
|
|
bool LookupHelper = true;
|
|
if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
|
|
Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
|
|
|
|
if (std::binary_search(std::begin(HardFloatLibCalls),
|
|
std::end(HardFloatLibCalls), Find))
|
|
LookupHelper = false;
|
|
else {
|
|
const char *Symbol = S->getSymbol();
|
|
Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
|
|
const Mips16HardFloatInfo::FuncSignature *Signature =
|
|
Mips16HardFloatInfo::findFuncSignature(Symbol);
|
|
if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
|
|
FuncInfo->StubsNeeded.end()))) {
|
|
FuncInfo->StubsNeeded[Symbol] = Signature;
|
|
//
|
|
// S2 is normally saved if the stub is for a function which
|
|
// returns a float or double value and is not otherwise. This is
|
|
// because more work is required after the function the stub
|
|
// is calling completes, and so the stub cannot directly return
|
|
// and the stub has no stack space to store the return address so
|
|
// S2 is used for that purpose.
|
|
// In order to take advantage of not saving S2, we need to also
|
|
// optimize the call in the stub and this requires some further
|
|
// functionality in MipsAsmPrinter which we don't have yet.
|
|
// So for now we always save S2. The optimization will be done
|
|
// in a follow-on patch.
|
|
//
|
|
if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
|
|
FuncInfo->setSaveS2();
|
|
}
|
|
// one more look at list of intrinsics
|
|
const Mips16IntrinsicHelperType *Helper =
|
|
llvm::lower_bound(Mips16IntrinsicHelper, IntrinsicFind);
|
|
if (Helper != std::end(Mips16IntrinsicHelper) &&
|
|
*Helper == IntrinsicFind) {
|
|
Mips16HelperFunction = Helper->Helper;
|
|
NeedMips16Helper = true;
|
|
LookupHelper = false;
|
|
}
|
|
|
|
}
|
|
} else if (GlobalAddressSDNode *G =
|
|
dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
|
|
Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
|
|
G->getGlobal()->getName().data() };
|
|
|
|
if (std::binary_search(std::begin(HardFloatLibCalls),
|
|
std::end(HardFloatLibCalls), Find))
|
|
LookupHelper = false;
|
|
}
|
|
if (LookupHelper)
|
|
Mips16HelperFunction =
|
|
getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
|
|
}
|
|
|
|
SDValue JumpTarget = Callee;
|
|
|
|
// T9 should contain the address of the callee function if
|
|
// -relocation-model=pic or it is an indirect call.
|
|
if (IsPICCall || !GlobalOrExternal) {
|
|
unsigned V0Reg = Mips::V0;
|
|
if (NeedMips16Helper) {
|
|
RegsToPass.push_front(std::make_pair(V0Reg, Callee));
|
|
JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
|
|
getPointerTy(DAG.getDataLayout()));
|
|
ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
|
|
JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
|
|
MipsII::MO_GOT, Chain,
|
|
FuncInfo->callPtrInfo(S->getSymbol()));
|
|
} else
|
|
RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
|
|
}
|
|
|
|
Ops.push_back(JumpTarget);
|
|
|
|
MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
|
|
InternalLinkage, IsCallReloc, CLI, Callee,
|
|
Chain);
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
// true/false values to select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator It = ++BB->getIterator();
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// setcc r1, r2, r3
|
|
// bNE r1, r0, copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(It, copy0MBB);
|
|
F->insert(It, sinkMBB);
|
|
|
|
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
|
sinkMBB->splice(sinkMBB->begin(), BB,
|
|
std::next(MachineBasicBlock::iterator(MI)), BB->end());
|
|
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
BuildMI(BB, DL, TII->get(Opc))
|
|
.addReg(MI.getOperand(3).getReg())
|
|
.addMBB(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
|
|
.addReg(MI.getOperand(1).getReg())
|
|
.addMBB(thisMBB)
|
|
.addReg(MI.getOperand(2).getReg())
|
|
.addMBB(copy0MBB);
|
|
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
// true/false values to select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator It = ++BB->getIterator();
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// setcc r1, r2, r3
|
|
// bNE r1, r0, copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(It, copy0MBB);
|
|
F->insert(It, sinkMBB);
|
|
|
|
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
|
sinkMBB->splice(sinkMBB->begin(), BB,
|
|
std::next(MachineBasicBlock::iterator(MI)), BB->end());
|
|
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
BuildMI(BB, DL, TII->get(Opc2))
|
|
.addReg(MI.getOperand(3).getReg())
|
|
.addReg(MI.getOperand(4).getReg());
|
|
BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
|
|
.addReg(MI.getOperand(1).getReg())
|
|
.addMBB(thisMBB)
|
|
.addReg(MI.getOperand(2).getReg())
|
|
.addMBB(copy0MBB);
|
|
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
|
|
MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
// true/false values to select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator It = ++BB->getIterator();
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// setcc r1, r2, r3
|
|
// bNE r1, r0, copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(It, copy0MBB);
|
|
F->insert(It, sinkMBB);
|
|
|
|
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
|
sinkMBB->splice(sinkMBB->begin(), BB,
|
|
std::next(MachineBasicBlock::iterator(MI)), BB->end());
|
|
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
BuildMI(BB, DL, TII->get(Opc2))
|
|
.addReg(MI.getOperand(3).getReg())
|
|
.addImm(MI.getOperand(4).getImm());
|
|
BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
|
|
.addReg(MI.getOperand(1).getReg())
|
|
.addMBB(thisMBB)
|
|
.addReg(MI.getOperand(2).getReg())
|
|
.addMBB(copy0MBB);
|
|
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
|
|
MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
Register regX = MI.getOperand(0).getReg();
|
|
Register regY = MI.getOperand(1).getReg();
|
|
MachineBasicBlock *target = MI.getOperand(2).getMBB();
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
|
|
.addReg(regX)
|
|
.addReg(regY);
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
|
|
unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
|
|
MachineInstr &MI, MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
Register regX = MI.getOperand(0).getReg();
|
|
int64_t imm = MI.getOperand(1).getImm();
|
|
MachineBasicBlock *target = MI.getOperand(2).getMBB();
|
|
unsigned CmpOpc;
|
|
if (isUInt<8>(imm))
|
|
CmpOpc = CmpiOpc;
|
|
else if ((!ImmSigned && isUInt<16>(imm)) ||
|
|
(ImmSigned && isInt<16>(imm)))
|
|
CmpOpc = CmpiXOpc;
|
|
else
|
|
llvm_unreachable("immediate field not usable");
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
static unsigned Mips16WhichOp8uOr16simm
|
|
(unsigned shortOp, unsigned longOp, int64_t Imm) {
|
|
if (isUInt<8>(Imm))
|
|
return shortOp;
|
|
else if (isInt<16>(Imm))
|
|
return longOp;
|
|
else
|
|
llvm_unreachable("immediate field not usable");
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
Register CC = MI.getOperand(0).getReg();
|
|
Register regX = MI.getOperand(1).getReg();
|
|
Register regY = MI.getOperand(2).getReg();
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
|
|
.addReg(regX)
|
|
.addReg(regY);
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
|
|
.addReg(Mips::T8);
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
|
|
MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
if (DontExpandCondPseudos16)
|
|
return BB;
|
|
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
|
Register CC = MI.getOperand(0).getReg();
|
|
Register regX = MI.getOperand(1).getReg();
|
|
int64_t Imm = MI.getOperand(2).getImm();
|
|
unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
|
|
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
|
|
.addReg(Mips::T8);
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
|
|
}
|