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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
llvm-mirror/test
Ayke van Laethem 283f599fca [AVR] Fix miscompilation of zext + add
Code like the following:

    define i32 @foo(i32 %a, i1 zeroext %b) addrspace(1) {
    entry:
      %conv = zext i1 %b to i32
      %add = add nsw i32 %conv, %a
      ret i32 %add
    }

Would compile to the following (incorrect) code:

    foo:
        mov     r18, r20
        clr     r19
        add     r22, r18
        adc     r23, r19
        sbci    r24, 0
        sbci    r25, 0
        ret

Those sbci instructions are clearly wrong, they should have been adc
instructions.

This commit improves codegen to use adc instead:

    foo:
        mov     r18, r20
        clr     r19
        ldi     r20, 0
        ldi     r21, 0
        add     r22, r18
        adc     r23, r19
        adc     r24, r20
        adc     r25, r21
        ret

This code is not optimal (it could be just 5 instructions instead of the
current 9) but at least it doesn't miscompile.

Differential Revision: https://reviews.llvm.org/D78439
2020-06-18 16:51:37 +02:00
..
Analysis [SVE] Add flag to specify SVE register size, using this to calculate legal vector types. 2020-06-18 12:11:16 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen [AVR] Fix miscompilation of zext + add 2020-06-18 16:51:37 +02:00
DebugInfo [CodeView] Fix generated command-line expansion in LF_BUILDINFO. Fix the 'pdb' entry which was previously a null reference, now an empty string. 2020-06-18 10:07:30 -04:00
Demangle
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker [IR] Add missing GlobalAlias copying of ThreadLocalMode attribute 2020-06-16 20:15:27 -07:00
LTO
MachineVerifier
MC [AVR] Implement disassembly of 32-bit instructions 2020-06-18 11:26:58 +02:00
Object [llvm-readobj] set --elf-cg-profile as alias of --cg-profile 2020-06-17 11:24:45 -07:00
ObjectYAML [DWARFYAML][debug_abbrev] Make the abbreviation code optional. 2020-06-18 13:02:54 +08:00
Other [CallPrinter] Adding heat coloring to CallPrinter 2020-06-16 21:15:29 +00:00
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86
tools [DWARFYAML][debug_abbrev] Make the abbreviation code optional. 2020-06-18 13:02:54 +08:00
Transforms [Matrix] Use alignment info when lowering loads/stores. 2020-06-18 13:19:31 +01:00
Unit
Verifier [Matrix] Update load/store intrinsics. 2020-06-18 09:44:52 +01:00
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh