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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
43 lines
2.2 KiB
LLVM
43 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
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; PR5411
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%bar = type { %quad, float, float, [3 x %quux*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
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%baz = type { %bar*, i32 }
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%foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz }
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%quad = type { [4 x float] }
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%quux = type { %quad, %quad }
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%quuz = type { [4 x %quux*], [4 x float], i32 }
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define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quux* %a, %quux* %b, %quux* %c, i8 zeroext %forced) {
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entry:
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br i1 undef, label %bb85, label %bb
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bb: ; preds = %entry
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%0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2]
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%1 = load float, float* undef, align 4 ; <float> [#uses=1]
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%2 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
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%3 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
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%4 = load float, float* %0, align 4 ; <float> [#uses=3]
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%5 = fmul float %4, %2 ; <float> [#uses=1]
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%6 = fsub float %3, %5 ; <float> [#uses=1]
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%7 = fmul float %4, undef ; <float> [#uses=1]
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%8 = fsub float %7, undef ; <float> [#uses=1]
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%9 = fmul float undef, %2 ; <float> [#uses=1]
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%10 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
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%11 = fsub float %9, %10 ; <float> [#uses=1]
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%12 = fmul float undef, %6 ; <float> [#uses=1]
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%13 = fmul float 0.000000e+00, %8 ; <float> [#uses=1]
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%14 = fadd float %12, %13 ; <float> [#uses=1]
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%15 = fmul float %1, %11 ; <float> [#uses=1]
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%16 = fadd float %14, %15 ; <float> [#uses=1]
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%17 = select i1 undef, float undef, float %16 ; <float> [#uses=1]
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%18 = fdiv float %17, 0.000000e+00 ; <float> [#uses=1]
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store float %18, float* undef, align 4
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%19 = fmul float %4, undef ; <float> [#uses=1]
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store float %19, float* %0, align 4
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ret %bar* null
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bb85: ; preds = %entry
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ret %bar* null
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}
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