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09ef958be1
This patch upstreams support for the Armv8.6-a Matrix Multiplication Extension. A summary of the features can be found here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a This patch includes: - Assembly support for AArch32 - Intrinsics Support for AArch32 Neon Intrinsics for Matrix Multiplication Note: these extensions are optional in the 8.6a architecture and so have to be enabled by default No additional IR types or C Types are needed for this extension. This is part of a patch series, starting with BFloat16 support and the other components in the armv8.6a extension (in previous patches linked in phabricator) Based on work by: - Luke Geeson - Oliver Stannard - Luke Cheeseman Reviewers: t.p.northover, miyuki Reviewed By: miyuki Subscribers: miyuki, ostannard, kristof.beyls, hiraditya, danielkiss, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D77872
84 lines
3.6 KiB
LLVM
84 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=arm-none-linux-gnu -mattr=+neon,+i8mm -float-abi=hard < %s -o -| FileCheck %s
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define <4 x i32> @smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
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entry:
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; CHECK-LABEL: smmla.v4i32.v16i8
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; CHECK: vsmmla.s8 q0, q1, q2
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%vmmla1.i = tail call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #3
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ret <4 x i32> %vmmla1.i
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}
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define <4 x i32> @ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
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entry:
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; CHECK-LABEL: ummla.v4i32.v16i8
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; CHECK: vummla.u8 q0, q1, q2
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%vmmla1.i = tail call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #3
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ret <4 x i32> %vmmla1.i
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}
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define <4 x i32> @usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
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entry:
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; CHECK-LABEL: usmmla.v4i32.v16i8
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; CHECK: vusmmla.s8 q0, q1, q2
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%vusmmla1.i = tail call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #3
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ret <4 x i32> %vusmmla1.i
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}
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define <2 x i32> @usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {
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entry:
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; CHECK-LABEL: usdot.v2i32.v8i8
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; CHECK: vusdot.s8 d0, d1, d2
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%vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) #3
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ret <2 x i32> %vusdot1.i
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}
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define <2 x i32> @usdot_lane.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {
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entry:
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; CHECK-LABEL: usdot_lane.v2i32.v8i8
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; CHECK: vusdot.s8 d0, d1, d2[0]
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%0 = bitcast <8 x i8> %b to <2 x i32>
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%shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer
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%1 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %1) #3
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ret <2 x i32> %vusdot1.i
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}
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define <2 x i32> @sudot_lane.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {
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entry:
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; CHECK-LABEL: sudot_lane.v2i32.v8i8
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; CHECK: vsudot.u8 d0, d1, d2[0]
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%0 = bitcast <8 x i8> %b to <2 x i32>
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%shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer
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%1 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8 x i8> %a) #3
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ret <2 x i32> %vusdot1.i
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}
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define <4 x i32> @usdotq_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {
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entry:
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; CHECK-LABEL: usdotq_lane.v4i32.v16i8
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; CHECK: vusdot.s8 q0, q1, d4[0]
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%0 = bitcast <8 x i8> %b to <2 x i32>
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%shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> zeroinitializer
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%1 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vusdot1.i = tail call <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %1) #3
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ret <4 x i32> %vusdot1.i
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}
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define <4 x i32> @sudotq_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {
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entry:
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; CHECK-LABEL: sudotq_lane.v4i32.v16i8
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; CHECK: vsudot.u8 q0, q1, d4[0]
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%0 = bitcast <8 x i8> %b to <2 x i32>
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%shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> zeroinitializer
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%1 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vusdot1.i = tail call <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %1, <16 x i8> %a) #3
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ret <4 x i32> %vusdot1.i
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}
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declare <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2
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declare <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2
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declare <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2
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declare <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>) #2
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declare <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2
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