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https://github.com/RPCS3/llvm-mirror.git
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b9ecf8a3ee
This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
141 lines
5.3 KiB
LLVM
141 lines
5.3 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst2i8:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vst2.8 {d16, d17}, [r0:64]
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%tmp1 = load <8 x i8>, <8 x i8>* %B
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call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
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ret void
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}
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;Check for a post-increment updating store with register increment.
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define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
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;CHECK-LABEL: vst2i8_update:
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;CHECK: vst2.8 {d16, d17}, [r1], r2
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%A = load i8*, i8** %ptr
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%tmp1 = load <8 x i8>, <8 x i8>* %B
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call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4)
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%tmp2 = getelementptr i8, i8* %A, i32 %inc
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store i8* %tmp2, i8** %ptr
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ret void
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}
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define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst2i16:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vst2.16 {d16, d17}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>, <4 x i16>* %B
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call void @llvm.arm.neon.vst2.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
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ret void
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}
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define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst2i32:
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;CHECK: vst2.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>, <2 x i32>* %B
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call void @llvm.arm.neon.vst2.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst2f(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst2f:
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;CHECK: vst2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>, <2 x float>* %B
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call void @llvm.arm.neon.vst2.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
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ret void
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}
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define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
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;CHECK-LABEL: vst2i64:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vst1.64 {d16, d17}, [r0:128]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <1 x i64>, <1 x i64>* %B
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call void @llvm.arm.neon.vst2.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
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;CHECK-LABEL: vst2i64_update:
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;CHECK: vst1.64 {d16, d17}, [r1:64]!
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%A = load i64*, i64** %ptr
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <1 x i64>, <1 x i64>* %B
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call void @llvm.arm.neon.vst2.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8)
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%tmp2 = getelementptr i64, i64* %A, i32 2
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store i64* %tmp2, i64** %ptr
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ret void
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}
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define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vst2Qi8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
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%tmp1 = load <16 x i8>, <16 x i8>* %B
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call void @llvm.arm.neon.vst2.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
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ret void
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}
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define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst2Qi16:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>, <8 x i16>* %B
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call void @llvm.arm.neon.vst2.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16)
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ret void
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}
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define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst2Qi32:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>, <4 x i32>* %B
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call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64)
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ret void
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}
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define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst2Qf:
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;CHECK: vst2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>, <4 x float>* %B
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call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
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ret void
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}
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define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst2update:
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;CHECK: vst2.16 {d16, d17}, [r0]!
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%tmp1 = load <4 x i16>, <4 x i16>* %B
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tail call void @llvm.arm.neon.vst2.p0i8.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
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%t5 = getelementptr inbounds i8, i8* %out, i32 16
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ret i8* %t5
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}
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define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
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;CHECK-LABEL: vst2update2:
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;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
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%tmp1 = load <4 x float>, <4 x float>* %this
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call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
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%tmp2 = getelementptr inbounds i8, i8* %out, i32 32
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ret i8* %tmp2
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}
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declare void @llvm.arm.neon.vst2.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
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