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a619e90821
The instruction addi is usually used to post increase the loop indvar, which looks like this: label_X: load x, base(i) ... y = op x ... i = addi i, 1 goto label_X However, for PowerPC, if there are too many vsx instructions that between y = op x and i = addi i, 1, it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve. Reviewed By: jji Differential Revision: https://reviews.llvm.org/D80269
114 lines
3.5 KiB
LLVM
114 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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@.str.28 = external unnamed_addr constant [69 x i8], align 1
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define void @print_res() nounwind {
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; CHECK-LABEL: print_res:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -128(1)
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: addi 3, 3, -1
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; CHECK-NEXT: clrldi 4, 3, 32
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; CHECK-NEXT: cmplwi 3, 1
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: li 4, 2
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; CHECK-NEXT: addi 3, 3, -1
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; CHECK-NEXT: cmpldi 3, 2
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; CHECK-NEXT: isellt 3, 3, 4
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: addi 3, 3, 1
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; CHECK-NEXT: mtctr 3
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: li 7, -1
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: lbz 5, 0(5)
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; CHECK-NEXT: bdz .LBB0_6
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: addi 3, 3, 1
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; CHECK-NEXT: addi 8, 7, -1
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; CHECK-NEXT: xori 6, 5, 84
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; CHECK-NEXT: clrldi 5, 7, 32
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; CHECK-NEXT: lbz 5, 0(5)
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; CHECK-NEXT: bdz .LBB0_5
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: addi 3, 3, 1
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; CHECK-NEXT: cntlzw 6, 6
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; CHECK-NEXT: srwi 7, 6, 5
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; CHECK-NEXT: xori 6, 5, 84
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; CHECK-NEXT: clrldi 5, 8, 32
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; CHECK-NEXT: addi 8, 8, -1
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; CHECK-NEXT: lbz 5, 0(5)
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; CHECK-NEXT: bdz .LBB0_4
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: addi 3, 3, 1
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; CHECK-NEXT: clrldi 10, 8, 32
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; CHECK-NEXT: addi 8, 8, -1
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; CHECK-NEXT: cntlzw 9, 6
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; CHECK-NEXT: xori 6, 5, 84
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; CHECK-NEXT: lbz 5, 0(10)
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; CHECK-NEXT: add 4, 4, 7
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; CHECK-NEXT: srwi 7, 9, 5
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; CHECK-NEXT: bdnz .LBB0_3
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: add 4, 4, 7
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: cntlzw 6, 6
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; CHECK-NEXT: srwi 6, 6, 5
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; CHECK-NEXT: add 4, 4, 6
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; CHECK-NEXT: .LBB0_6:
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; CHECK-NEXT: xori 5, 5, 84
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; CHECK-NEXT: cntlzw 5, 5
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: std 3, 104(1)
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: li 7, 0
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; CHECK-NEXT: li 8, 3
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; CHECK-NEXT: srwi 5, 5, 5
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; CHECK-NEXT: add 4, 4, 5
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: std 5, 120(1)
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; CHECK-NEXT: li 5, 3
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; CHECK-NEXT: std 5, 96(1)
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; CHECK-NEXT: clrldi 6, 4, 32
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; CHECK-NEXT: li 4, 3
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: li 10, 0
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; CHECK-NEXT: bl printf
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; CHECK-NEXT: nop
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%1 = load i32, i32* undef, align 4
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%2 = add i32 %1, -1
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%3 = zext i32 %2 to i64
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%4 = zext i32 3 to i64
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br label %5
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5: ; preds = %5, %0
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%6 = phi i64 [ %16, %5 ], [ 0, %0 ]
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%7 = phi i32 [ %15, %5 ], [ 0, %0 ]
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%8 = trunc i64 %6 to i32
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%9 = sub i32 0, %8
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%10 = zext i32 %9 to i64
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%11 = getelementptr inbounds i8, i8* null, i64 %10
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%12 = load i8, i8* %11, align 1
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%13 = icmp eq i8 %12, 84
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%14 = zext i1 %13 to i32
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%15 = add i32 %7, %14
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%16 = add nuw nsw i64 %6, 1
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%17 = icmp ult i64 %16, %3
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%18 = icmp ult i64 %16, %4
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%19 = and i1 %18, %17
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br i1 %19, label %5, label %20
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20: ; preds = %5
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%21 = trunc i64 %16 to i32
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call void (i8*, ...) @printf(i8* getelementptr inbounds ([69 x i8], [69 x i8]* @.str.28, i64 0, i64 0), i32 zeroext 3, i32 zeroext undef, i32 zeroext %15, i32 zeroext undef, i32 zeroext 3, i8* undef, i32 zeroext undef, i32 zeroext 3, i32 zeroext %21, i8* undef, i32 zeroext undef) #1
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unreachable
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}
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declare void @printf(i8*, ...) local_unnamed_addr #0
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