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437bb9ba7e
https://llvm.org/bugs/show_bug.cgi?id=24766#c2 This removes a hack that was added for the benefit of x86 codegen. It prevented shrinking the switch condition even to smaller legal (DataLayout) types. We have a safety mechanism in CGP after: http://reviews.llvm.org/rL251857 ...so we're free to use the optimal (smallest) IR type now. Differential Revision: http://reviews.llvm.org/D12965 llvm-svn: 274233
25 lines
517 B
LLVM
25 lines
517 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; Provide legal integer types.
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target datalayout = "n8:16:32:64"
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define void @PR21651() {
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; CHECK-LABEL: @PR21651(
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; CHECK-NEXT: switch i1 false, label %out [
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; CHECK-NEXT: i1 false, label %out
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; CHECK-NEXT: i1 true, label %out
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; CHECK-NEXT: ]
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; CHECK: out:
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; CHECK-NEXT: ret void
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;
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switch i2 0, label %out [
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i2 0, label %out
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i2 1, label %out
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]
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out:
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ret void
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}
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