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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
217 lines
7.8 KiB
C++
217 lines
7.8 KiB
C++
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the base ARM implementation of TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include <cstdint>
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#define GET_REGINFO_HEADER
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#include "ARMGenRegisterInfo.inc"
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namespace llvm {
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class LiveIntervals;
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/// Register allocation hints.
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namespace ARMRI {
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enum {
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RegPairOdd = 1,
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RegPairEven = 2
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};
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} // end namespace ARMRI
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/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
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/// or a stack/pc register that we should push/pop.
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static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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case LR: case SP: case PC:
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return true;
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case R8: case R9: case R10: case R11: case R12:
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// For iOS we want r7 and lr to be next to each other.
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return !isIOS;
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default:
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return false;
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}
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}
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static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
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using namespace ARM;
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switch (Reg) {
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case R8: case R9: case R10: case R11: case R12:
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// iOS has this second area.
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return isIOS;
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default:
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return false;
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}
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}
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static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
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using namespace ARM;
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switch (Reg) {
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case D15: case D14: case D13: case D12:
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case D11: case D10: case D9: case D8:
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case D7: case D6: case D5: case D4:
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case D3: case D2: case D1: case D0:
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case D31: case D30: case D29: case D28:
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case D27: case D26: case D25: case D24:
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case D23: case D22: case D21: case D20:
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case D19: case D18: case D17: case D16:
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return true;
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default:
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return false;
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}
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}
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static inline bool isCalleeSavedRegister(unsigned Reg,
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const MCPhysReg *CSRegs) {
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for (unsigned i = 0; CSRegs[i]; ++i)
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if (Reg == CSRegs[i])
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return true;
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return false;
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}
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class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
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protected:
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/// BasePtr - ARM physical register used as a base ptr in complex stack
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/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
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/// variable size stack objects.
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unsigned BasePtr = ARM::R6;
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// Can be only subclassed.
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explicit ARMBaseRegisterInfo();
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// Return the opcode that implements 'Op', or 0 if no opcode
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unsigned getOpcode(int Op) const;
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public:
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const MCPhysReg *
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getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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const uint32_t *getNoPreservedMask() const override;
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const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
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const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
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/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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/// case that 'returned' is on an i32 first argument if the calling convention
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/// is one that can (partially) model this attribute with a preserved mask
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/// (i.e. it is a calling convention that uses the same register for the first
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/// i32 argument and an i32 return value)
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///
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/// Should return NULL in the case that the calling convention does not have
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/// this property
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const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool isAsmClobberable(const MachineFunction &MF,
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unsigned PhysReg) const override;
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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bool getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const override;
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void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const override;
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int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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int Idx) const override;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool cannotEliminateFrame(const MachineFunction &MF) const;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getBaseRegister() const { return BasePtr; }
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bool isLowRegister(unsigned Reg) const;
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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virtual void
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emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
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int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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unsigned PredReg = 0,
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unsigned MIFlags = MachineInstr::NoFlags) const;
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/// Code Generation virtual methods...
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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/// SrcRC and DstRC will be morphed into NewRC if this returns true
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bool shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC,
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LiveIntervals &LIS) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
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