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156 lines
5.4 KiB
TableGen
156 lines
5.4 KiB
TableGen
//===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARM system-registers
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//===----------------------------------------------------------------------===//
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// M-Class System Registers.
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// 'Mask' bits create unique keys for searches.
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//
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class MClassSysReg<bits<1> UniqMask1,
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bits<1> UniqMask2,
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bits<1> UniqMask3,
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bits<12> Enc12,
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string name> : SearchableTable {
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let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
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string Name;
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bits<13> M1Encoding12;
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bits<10> M2M3Encoding8;
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bits<12> Encoding;
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let Name = name;
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let EnumValueField = "M1Encoding12";
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let EnumValueField = "M2M3Encoding8";
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let EnumValueField = "Encoding";
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let M1Encoding12{12} = UniqMask1;
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let M1Encoding12{11-00} = Enc12;
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let Encoding = Enc12;
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let M2M3Encoding8{9} = UniqMask2;
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let M2M3Encoding8{8} = UniqMask3;
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let M2M3Encoding8{7-0} = Enc12{7-0};
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code Requires = [{ {} }];
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}
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// [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr.
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// Mask1 Mask2 Mask3 Enc12, Name
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let Requires = [{ {ARM::FeatureDSP} }] in {
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def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">;
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def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">;
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def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">;
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def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">;
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def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">;
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def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">;
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def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">;
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def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">;
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}
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def : MClassSysReg<0, 0, 1, 0x800, "apsr">;
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def : MClassSysReg<1, 1, 0, 0x800, "apsr_nzcvq">;
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def : MClassSysReg<0, 0, 1, 0x801, "iapsr">;
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def : MClassSysReg<1, 1, 0, 0x801, "iapsr_nzcvq">;
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def : MClassSysReg<0, 0, 1, 0x802, "eapsr">;
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def : MClassSysReg<1, 1, 0, 0x802, "eapsr_nzcvq">;
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def : MClassSysReg<0, 0, 1, 0x803, "xpsr">;
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def : MClassSysReg<1, 1, 0, 0x803, "xpsr_nzcvq">;
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def : MClassSysReg<0, 0, 1, 0x805, "ipsr">;
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def : MClassSysReg<0, 0, 1, 0x806, "epsr">;
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def : MClassSysReg<0, 0, 1, 0x807, "iepsr">;
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def : MClassSysReg<0, 0, 1, 0x808, "msp">;
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def : MClassSysReg<0, 0, 1, 0x809, "psp">;
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let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
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def : MClassSysReg<0, 0, 1, 0x80a, "msplim">;
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def : MClassSysReg<0, 0, 1, 0x80b, "psplim">;
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}
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def : MClassSysReg<0, 0, 1, 0x810, "primask">;
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let Requires = [{ {ARM::HasV7Ops} }] in {
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def : MClassSysReg<0, 0, 1, 0x811, "basepri">;
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def : MClassSysReg<0, 0, 1, 0x812, "basepri_max">;
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def : MClassSysReg<0, 0, 1, 0x813, "faultmask">;
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}
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def : MClassSysReg<0, 0, 1, 0x814, "control">;
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let Requires = [{ {ARM::Feature8MSecExt} }] in {
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def : MClassSysReg<0, 0, 1, 0x888, "msp_ns">;
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def : MClassSysReg<0, 0, 1, 0x889, "psp_ns">;
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}
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let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
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def : MClassSysReg<0, 0, 1, 0x88a, "msplim_ns">;
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def : MClassSysReg<0, 0, 1, 0x88b, "psplim_ns">;
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}
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def : MClassSysReg<0, 0, 1, 0x890, "primask_ns">;
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let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
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def : MClassSysReg<0, 0, 1, 0x891, "basepri_ns">;
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def : MClassSysReg<0, 0, 1, 0x893, "faultmask_ns">;
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}
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let Requires = [{ {ARM::Feature8MSecExt} }] in {
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def : MClassSysReg<0, 0, 1, 0x894, "control_ns">;
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def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">;
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}
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// Banked Registers
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//
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class BankedReg<string name, bits<8> enc>
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: SearchableTable {
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string Name;
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bits<8> Encoding;
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let Name = name;
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let Encoding = enc;
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let SearchableFields = ["Name", "Encoding"];
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}
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// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
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// and bit 5 is R.
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def : BankedReg<"r8_usr", 0x00>;
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def : BankedReg<"r9_usr", 0x01>;
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def : BankedReg<"r10_usr", 0x02>;
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def : BankedReg<"r11_usr", 0x03>;
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def : BankedReg<"r12_usr", 0x04>;
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def : BankedReg<"sp_usr", 0x05>;
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def : BankedReg<"lr_usr", 0x06>;
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def : BankedReg<"r8_fiq", 0x08>;
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def : BankedReg<"r9_fiq", 0x09>;
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def : BankedReg<"r10_fiq", 0x0a>;
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def : BankedReg<"r11_fiq", 0x0b>;
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def : BankedReg<"r12_fiq", 0x0c>;
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def : BankedReg<"sp_fiq", 0x0d>;
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def : BankedReg<"lr_fiq", 0x0e>;
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def : BankedReg<"lr_irq", 0x10>;
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def : BankedReg<"sp_irq", 0x11>;
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def : BankedReg<"lr_svc", 0x12>;
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def : BankedReg<"sp_svc", 0x13>;
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def : BankedReg<"lr_abt", 0x14>;
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def : BankedReg<"sp_abt", 0x15>;
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def : BankedReg<"lr_und", 0x16>;
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def : BankedReg<"sp_und", 0x17>;
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def : BankedReg<"lr_mon", 0x1c>;
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def : BankedReg<"sp_mon", 0x1d>;
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def : BankedReg<"elr_hyp", 0x1e>;
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def : BankedReg<"sp_hyp", 0x1f>;
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def : BankedReg<"spsr_fiq", 0x2e>;
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def : BankedReg<"spsr_irq", 0x30>;
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def : BankedReg<"spsr_svc", 0x32>;
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def : BankedReg<"spsr_abt", 0x34>;
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def : BankedReg<"spsr_und", 0x36>;
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def : BankedReg<"spsr_mon", 0x3c>;
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def : BankedReg<"spsr_hyp", 0x3e>;
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