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llvm-mirror/test/MC
Philip Reames e0244827fe Align branches within 32-Byte boundary (NOP padding)
WARNING: If you're looking at this patch because you're looking for a full
performace mitigation of the Intel JCC Erratum, this is not it!

This is a preliminary patch on the patch towards mitigating the performance
regressions caused by Intel's microcode update for Jump Conditional Code
Erratum.  For context, see:
https://www.intel.com/content/www/us/en/support/articles/000055650.html

The patch adds the required assembler infrastructure and command line options
needed to exercise the logic for INTERNAL TESTING.  These are NOT public flags,
and should not be used for anything other than LLVM's own testing/debugging
purposes.  They are likely to change both in spelling and meaning.

WARNING: This patch is knowingly incorrect in some cornercases.  We need, and
do not yet provide, a mechanism to selective enable/disable the padding.
Conversation on this will continue in parellel with work on extending this
infrastructure to support prefix padding.

The goal here is to have the assembler align specific instructions such that
they neither cross or end at a 32 byte boundary.  The impacted instructions are:
a. Conditional jump.
b. Fused conditional jump.
c. Unconditional jump.
d. Indirect jump.
e. Ret.
f. Call.

The new options for llvm-mc are:
    -x86-align-branch-boundary=NUM aligns branches within NUM byte boundary.
    -x86-align-branch=TYPE[+TYPE...] specifies types of branches to align.

A new MCFragment type, MCBoundaryAlignFragment, is added, which may emit
NOP to align the fused/unfused branch.

alignBranchesBegin inserts MCBoundaryAlignFragment before instructions,
alignBranchesEnd marks the end of the branch to be aligned,
relaxBoundaryAlign grows or shrinks sizes of NOP to align the target branch.

Nop padding is disabled when the instruction may be rewritten by the linker,
such as TLS Call.

Process Note: I am landing a patch by skan as it has been LGTMed, and
continuing to iterate on the review is simply slowing us down at this point.
We can and will continue to iterate in tree.

Patch By: skan
Differential Revision: https://reviews.llvm.org/D70157
2019-12-20 11:35:50 -08:00
..
AArch64 [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly. 2019-11-28 15:31:59 +00:00
AMDGPU [AMDGPU][MC][GFX10] Enabled v_movrel*[sdwa|dpp|dpp8] opcodes 2019-11-18 17:23:40 +03:00
ARM [llvm-readelf] - Change letters used for SHF_ARM_PURECODE and SHF_X86_64_LARGE flags. 2019-12-18 11:31:58 +03:00
AsmParser MCObjectStreamer: assign MCSymbols in the dummy fragment to offset 0. 2019-11-16 09:52:07 -05:00
AVR Fixup AVR tests to reflect changes in addend format in llvm-objdump 2019-11-19 15:32:58 +00:00
BPF
COFF [MC] Produce proper section relative relocations for COFF in .debug_frame 2019-11-27 10:44:42 +02:00
Disassembler [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly. 2019-11-28 15:31:59 +00:00
ELF [llvm-readobj] - Fix letters used for dumping section types in GNU style. 2019-12-13 11:31:24 +03:00
Hexagon [llvm-mc] Add reportWarning() to MCContext 2019-08-08 19:13:23 +00:00
Lanai
MachO [ MC ] Match labels to existing fragments even when switching sections. 2019-12-18 09:55:54 -08:00
Mips [mips] Fix sc, scs, ll, lld instructions expanding 2019-11-27 00:43:25 +03:00
MSP430
PowerPC [MC][PowerPC] Fix a crash when redefining a symbol after .set 2019-12-13 09:31:54 -08:00
RISCV [RISCV] Don't crash on unsupported relocations 2019-12-19 17:21:30 +00:00
Sparc
SystemZ [SystemZ] Improve handling of huge PC relative immediate offsets. 2019-11-04 10:38:18 +01:00
WebAssembly [WebAssembly] Implement SIMD {i8x16,i16x8}.avgr_u instructions 2019-12-17 15:05:50 -08:00
X86 Align branches within 32-Byte boundary (NOP padding) 2019-12-20 11:35:50 -08:00