Shiva Chen e9661f6b8f [RISCV] Add new SchedRead SchedWrite ... The patch fixes some typos and introduces ReadFMemBase, ReadFSGNJ32, ReadFSGNJ64, WriteFSGNJ32, WriteFSGNJ64, ReadFMinMax32, ReadFMinMax64, WriteFMinMax32, WriteFMinMax64, so the target CPU with different pipeline model could use them to describe latency. Differential Revision: https://reviews.llvm.org/D75515		2020-03-10 00:12:27 +08:00
..
AsmParser	[MC] De-capitalize another set of MCStreamer::Emit* functions	2020-02-14 19:26:52 -08:00
Disassembler
MCTargetDesc	[NFC][RISCV] Fixing typo in comment.	2020-02-05 11:30:11 -08:00
TargetInfo
Utils	[RISCV] Support ABI checking with per function target-features	2020-01-22 08:12:28 -08:00
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td	[RISCV] Add support for save/restore of callee-saved registers via libcalls	2020-02-11 21:23:03 +00:00
RISCVAsmPrinter.cpp	[RISCV] Compress instructions based on function features	2020-02-28 11:52:55 +00:00
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandPseudoInsts.cpp
RISCVFrameLowering.cpp	ArrayRef'ize restoreCalleeSavedRegisters. NFCI.	2020-02-29 09:50:23 +01:00
RISCVFrameLowering.h	ArrayRef'ize restoreCalleeSavedRegisters. NFCI.	2020-02-29 09:50:23 +01:00
RISCVInstrFormats.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[NFC] unsigned->Register in storeRegTo/loadRegFromStack	2020-02-03 14:22:16 +01:00
RISCVInstrInfo.h	[NFC] unsigned->Register in storeRegTo/loadRegFromStack	2020-02-03 14:22:16 +01:00
RISCVInstrInfo.td	[RISCV] Add new SchedRead SchedWrite	2020-03-10 00:12:27 +08:00
RISCVInstrInfoA.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrInfoC.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td	[RISCV] Add new SchedRead SchedWrite	2020-03-10 00:12:27 +08:00
RISCVInstrInfoF.td	[RISCV] Add new SchedRead SchedWrite	2020-03-10 00:12:27 +08:00
RISCVInstrInfoM.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp	[RISCV] Implement mayBeEmittedAsTailCall for tail call optimization	2020-02-18 23:56:42 +08:00
RISCVISelLowering.h	[RISCV] Implement mayBeEmittedAsTailCall for tail call optimization	2020-02-18 23:56:42 +08:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h	[RISCV] Add support for save/restore of callee-saved registers via libcalls	2020-02-11 21:23:03 +00:00
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Correct the CallPreservedMask for the function call in an interrupt handler	2020-02-15 09:14:04 +08:00
RISCVRegisterInfo.h	[RISCV] Add support for save/restore of callee-saved registers via libcalls	2020-02-11 21:23:03 +00:00
RISCVRegisterInfo.td
RISCVSchedRocket32.td	[RISCV] Add new SchedRead SchedWrite	2020-03-10 00:12:27 +08:00
RISCVSchedRocket64.td	[RISCV] Add new SchedRead SchedWrite	2020-03-10 00:12:27 +08:00
RISCVSchedule.td	[RISCV] Add new SchedRead SchedWrite	2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp	Make llvm::StringRef to std::string conversions explicit.	2020-01-28 23:25:25 +01:00
RISCVSubtarget.h	[RISCV] Add support for save/restore of callee-saved registers via libcalls	2020-02-11 21:23:03 +00:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp	[RISCV] Check the target-abi module flag matches the option	2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h