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29ffba4b56
This can be seen as a follow up to commit 0ee439b705e82a4fe20e2, that changed the second argument of __powidf2, __powisf2 and __powitf2 in compiler-rt from si_int to int. That was to align with how those runtimes are defined in libgcc. One thing that seem to have been missing in that patch was to make sure that the rest of LLVM also handle that the argument now depends on the size of int (not using the si_int machine mode for 32-bit). When using __builtin_powi for a target with 16-bit int clang crashed. And when emitting libcalls to those rtlib functions, typically when lowering @llvm.powi), the backend would always prepare the exponent argument as an i32 which caused miscompiles when the rtlib was compiled with 16-bit int. The solution used here is to use an overloaded type for the second argument in @llvm.powi. This way clang can use the "correct" type when lowering __builtin_powi, and then later when emitting the libcall it is assumed that the type used in @llvm.powi matches the rtlib function. One thing that needed some extra attention was that when vectorizing calls several passes did not support that several arguments could be overloaded in the intrinsics. This patch allows overload of a scalar operand by adding hasVectorInstrinsicOverloadedScalarOpd, with an entry for powi. Differential Revision: https://reviews.llvm.org/D99439
58 lines
1.4 KiB
LLVM
58 lines
1.4 KiB
LLVM
; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
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declare double @llvm.powi.f64.i32(double, i32)
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declare float @llvm.powi.f32.i32(float, i32)
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define arm_aapcs_vfpcc double @d(double %d, i32 %i) {
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entry:
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%0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
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ret double %0
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}
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; CHECK-LABEL: d:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
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; CHECK-NEXT: b pow
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; CHECK-NOT: __powisf2
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define arm_aapcs_vfpcc float @f(float %f, i32 %i) {
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entry:
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%0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
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ret float %0
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}
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; CHECK-LABEL: f:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
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; CHECK-NEXT: b pow
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; CHECK-NOT: __powisf2
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define arm_aapcs_vfpcc float @g(double %d, i32 %i) {
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entry:
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%0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
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%conv = fptrunc double %0 to float
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ret float %conv
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}
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; CHECK-LABEL: g:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
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; CHECK-NEXT: bl pow
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; CHECK-NOT: bl __powidf2
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; CHECK-NEXT: vcvt.f32.f64 s0, d0
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define arm_aapcs_vfpcc double @h(float %f, i32 %i) {
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entry:
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%0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
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%conv = fpext float %0 to double
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ret double %conv
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}
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; CHECK-LABEL: h:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
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; CHECK-NEXT: bl powf
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; CHECK-NOT: bl __powisf2
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; CHECK-NEXT: vcvt.f64.f32 d0, s0
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