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0a8fb0b4d7
I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32) isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if the assertzexti32 has an additional user. If we add a one use check it would just cause a fcvt.lu followed by a sext.w when only need a fcvt.wu to satisfy both users. To mitigate this I've added custom isel and new ISD opcodes for fcvt.wu. This allows us to keep know it started life as a conversion to i32 without needing to match multiple nodes. ComputeNumSignBits has been taught that this new nodes produces 33 sign bits. To prevent regressions when we need to zero extend the result of an (i32 (fptoui X)), I've added a DAG combine to convert it to an (i64 (fptoui X)) before type legalization. In most cases this would happen in InstCombine, but a zero_extend can be created for function returns or arguments. To keep everything consistent I've added new nodes for fptosi as well. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D106346
188 lines
5.1 KiB
LLVM
188 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IF
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; This file exhaustively checks float<->i32 conversions. In general,
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; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
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; generated for an fpto[s|u]i conversion if the result doesn't fit in the
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; target type.
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define i32 @aext_fptosi(float %a) nounwind {
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; RV64IF-LABEL: aext_fptosi:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptosi(float %a) nounwind {
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; RV64IF-LABEL: sext_fptosi:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptosi(float %a) nounwind {
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; RV64IF-LABEL: zext_fptosi:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
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; RV64IF-NEXT: slli a0, a0, 32
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; RV64IF-NEXT: srli a0, a0, 32
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; RV64IF-NEXT: ret
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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define i32 @aext_fptoui(float %a) nounwind {
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; RV64IF-LABEL: aext_fptoui:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptoui float %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptoui(float %a) nounwind {
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; RV64IF-LABEL: sext_fptoui:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptoui float %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptoui(float %a) nounwind {
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; RV64IF-LABEL: zext_fptoui:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptoui float %a to i32
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ret i32 %1
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}
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define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
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; RV64IF-LABEL: bcvt_f32_to_aext_i32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
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; RV64IF-LABEL: bcvt_f32_to_sext_i32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
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; RV64IF-LABEL: bcvt_f32_to_zext_i32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: slli a0, a0, 32
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; RV64IF-NEXT: srli a0, a0, 32
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
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; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fadd.s ft0, ft0, ft1
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = trunc i64 %a to i32
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%2 = trunc i64 %b to i32
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%3 = bitcast i32 %1 to float
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%4 = bitcast i32 %2 to float
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%5 = fadd float %3, %4
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ret float %5
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}
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define float @uitofp_aext_i32_to_f32(i32 %a) nounwind {
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; RV64IF-LABEL: uitofp_aext_i32_to_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i32 %a to float
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ret float %1
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}
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define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind {
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; RV64IF-LABEL: uitofp_sext_i32_to_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i32 %a to float
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ret float %1
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}
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define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
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; RV64IF-LABEL: uitofp_zext_i32_to_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i32 %a to float
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ret float %1
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}
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define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
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; RV64IF-LABEL: sitofp_aext_i32_to_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i32 %a to float
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ret float %1
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}
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define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
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; RV64IF-LABEL: sitofp_sext_i32_to_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i32 %a to float
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ret float %1
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}
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define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
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; RV64IF-LABEL: sitofp_zext_i32_to_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i32 %a to float
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ret float %1
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}
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