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https://github.com/RPCS3/llvm-mirror.git
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2d325e321e
Until fairly recently the calling convention for IR half was not handled correctly in the ARM backend, meaning we needed to pass pointers that were loaded/stored. Now that that is fixed we can switch to using the type directly instead.
187 lines
6.7 KiB
LLVM
187 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vaddqr_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <4 x i32> undef, i32 %src2, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c = add <4 x i32> %src, %sp
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ret <4 x i32> %c
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}
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define arm_aapcs_vfpcc <8 x i16> @vaddqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vaddqr_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <8 x i16> undef, i16 %src2, i32 0
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%sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
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%c = add <8 x i16> %src, %sp
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ret <8 x i16> %c
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}
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define arm_aapcs_vfpcc <16 x i8> @vaddqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vaddqr_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i8 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <16 x i8> undef, i8 %src2, i32 0
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%sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
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%c = add <16 x i8> %src, %sp
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ret <16 x i8> %c
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}
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define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32_2(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vaddqr_v4i32_2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <4 x i32> undef, i32 %src2, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c = add <4 x i32> %sp, %src
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ret <4 x i32> %c
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}
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define arm_aapcs_vfpcc <8 x i16> @vaddqr_v8i16_2(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vaddqr_v8i16_2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <8 x i16> undef, i16 %src2, i32 0
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%sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
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%c = add <8 x i16> %sp, %src
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ret <8 x i16> %c
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}
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define arm_aapcs_vfpcc <16 x i8> @vaddqr_v16i8_2(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vaddqr_v16i8_2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i8 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <16 x i8> undef, i8 %src2, i32 0
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%sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
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%c = add <16 x i8> %sp, %src
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ret <16 x i8> %c
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}
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define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: vaddqr_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vadd.f32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <4 x float> undef, float %src2, i32 0
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%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
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%c = fadd <4 x float> %src, %sp
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ret <4 x float> %c
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}
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define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: vaddqr_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 r0, s4
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; CHECK-NEXT: vadd.f16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <8 x half> undef, half %src2, i32 0
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%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
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%c = fadd <8 x half> %src, %sp
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ret <8 x half> %c
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}
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define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32_2(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: vaddqr_v4f32_2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vadd.f32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <4 x float> undef, float %src2, i32 0
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%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
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%c = fadd <4 x float> %sp, %src
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ret <4 x float> %c
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}
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define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16_2(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: vaddqr_v8f16_2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 r0, s4
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; CHECK-NEXT: vadd.f16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%i = insertelement <8 x half> undef, half %src2, i32 0
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%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
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%c = fadd <8 x half> %sp, %src
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ret <8 x half> %c
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}
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define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32_3(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: vaddqr_v4f32_3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vadd.f32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%src2bc = bitcast float %src2 to i32
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%i = insertelement <4 x i32> undef, i32 %src2bc, i32 0
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%spbc = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%sp = bitcast <4 x i32> %spbc to <4 x float>
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%c = fadd <4 x float> %src, %sp
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ret <4 x float> %c
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}
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define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16_3(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: vaddqr_v8f16_3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 r0, s4
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; CHECK-NEXT: vadd.f16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%src2bc = bitcast half %src2 to i16
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%i = insertelement <8 x i16> undef, i16 %src2bc, i32 0
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%spbc = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
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%sp = bitcast <8 x i16> %spbc to <8 x half>
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%c = fadd <8 x half> %src, %sp
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ret <8 x half> %c
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}
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define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32_4(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: vaddqr_v4f32_4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vadd.f32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%src2bc = bitcast float %src2 to i32
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%i = insertelement <4 x i32> undef, i32 %src2bc, i32 0
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%spbc = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%sp = bitcast <4 x i32> %spbc to <4 x float>
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%c = fadd <4 x float> %sp, %src
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ret <4 x float> %c
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}
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define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16_4(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: vaddqr_v8f16_4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 r0, s4
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; CHECK-NEXT: vadd.f16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%src2bc = bitcast half %src2 to i16
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%i = insertelement <8 x i16> undef, i16 %src2bc, i32 0
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%spbc = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
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%sp = bitcast <8 x i16> %spbc to <8 x half>
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%c = fadd <8 x half> %sp, %src
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ret <8 x half> %c
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}
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