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deba7b1d7c
ISD::ROTL/ROTR rotation values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits. Differential Revision: https://reviews.llvm.org/D76201
40 lines
998 B
LLVM
40 lines
998 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
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; RUN: llc < %s -mtriple=thumb-eabi | FileCheck %s -check-prefix=THUMB1
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define i32 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror.w r0, r0, #22
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; CHECK-NEXT: bx lr
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;
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; THUMB1-LABEL: f1:
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; THUMB1: @ %bb.0:
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; THUMB1-NEXT: movs r1, #22
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; THUMB1-NEXT: rors r0, r1
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; THUMB1-NEXT: bx lr
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%l8 = shl i32 %a, 10
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%r8 = lshr i32 %a, 22
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%tmp = or i32 %l8, %r8
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ret i32 %tmp
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}
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define i32 @f2(i32 %v, i32 %nbits) {
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; CHECK-LABEL: f2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: rors r0, r1
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; CHECK-NEXT: bx lr
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;
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; THUMB1-LABEL: f2:
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; THUMB1: @ %bb.0: @ %entry
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; THUMB1-NEXT: rors r0, r1
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; THUMB1-NEXT: bx lr
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entry:
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%and = and i32 %nbits, 31
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%shr = lshr i32 %v, %and
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%sub = sub i32 32, %and
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%shl = shl i32 %v, %sub
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%or = or i32 %shl, %shr
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ret i32 %or
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}
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