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4115608e9d
Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D91703
23 lines
1.1 KiB
TableGen
23 lines
1.1 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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let TargetPrefix = "mytarget" in {
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def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
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}
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// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
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// GISEL-NEXT: // MIs[0] Operand 0
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// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep0,
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// GISEL-NEXT: // MIs[0] src
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// GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1,
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// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIPFP_I64_Predicate_tuimm9,
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// GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_tuimm9>>:$src) => (SLEEP0 (timm:{ *:[i32] }):$src)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SLEEP0,
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
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def tuimm9 : TImmLeaf<i32, [{ return isUInt<9>(Imm); }]>;
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def SLEEP0 : I<(outs), (ins i32imm:$src),
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[(int_mytarget_sleep0 tuimm9:$src)]
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>;
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