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https://github.com/RPCS3/llvm-mirror.git
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eb30ce19c4
These intrinsics, not the icmp+select are the canonical form nowadays, so we might as well directly emit them. This should not cause any regressions, but if it does, then then they would needed to be fixed regardless. Note that this doesn't deal with `SCEVExpander::isHighCostExpansion()`, but that is a pessimization, not a correctness issue. Additionally, the non-intrinsic form has issues with undef, see https://reviews.llvm.org/D88287#2587863
225 lines
9.8 KiB
LLVM
225 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -indvars -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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; IV with constant start, preinc and postinc sign extends, with and without NSW.
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; IV rewrite only removes one sext. WidenIVs removes all three.
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define void @postincConstIV(i8* %base, i32 %limit) nounwind {
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; CHECK-LABEL: @postincConstIV(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[LIMIT:%.*]], i32 0)
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; CHECK-NEXT: [[TMP0:%.*]] = add nuw i32 [[SMAX]], 1
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store i8 0, i8* [[PREADR]], align 1
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i8 0, i8* [[POSTADR]], align 1
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; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr inbounds i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]], align 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: br label [[RETURN:%.*]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ %postiv, %loop ], [ 0, %entry ]
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%ivnsw = phi i32 [ %postivnsw, %loop ], [ 0, %entry ]
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%preofs = sext i32 %iv to i64
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%preadr = getelementptr i8, i8* %base, i64 %preofs
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store i8 0, i8* %preadr
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%postiv = add i32 %iv, 1
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%postofs = sext i32 %postiv to i64
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%postadr = getelementptr i8, i8* %base, i64 %postofs
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store i8 0, i8* %postadr
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%postivnsw = add nsw i32 %ivnsw, 1
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%postofsnsw = sext i32 %postivnsw to i64
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%postadrnsw = getelementptr inbounds i8, i8* %base, i64 %postofsnsw
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store i8 0, i8* %postadrnsw
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%cond = icmp sgt i32 %limit, %iv
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br i1 %cond, label %loop, label %exit
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exit:
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br label %return
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return:
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ret void
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}
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; IV with nonconstant start, preinc and postinc sign extends,
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; with and without NSW.
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; As with postincConstIV, WidenIVs removes all three sexts.
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define void @postincVarIV(i8* %base, i32 %init, i32 %limit) nounwind {
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; CHECK-LABEL: @postincVarIV(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[PRECOND:%.*]] = icmp sgt i32 [[LIMIT:%.*]], [[INIT:%.*]]
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; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[RETURN:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[INIT]] to i64
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[LIMIT]] to i64
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store i8 0, i8* [[PREADR]], align 1
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i8 0, i8* [[POSTADR]], align 1
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; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]], align 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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entry:
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%precond = icmp sgt i32 %limit, %init
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br i1 %precond, label %loop, label %return
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loop:
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%iv = phi i32 [ %postiv, %loop ], [ %init, %entry ]
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%ivnsw = phi i32 [ %postivnsw, %loop ], [ %init, %entry ]
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%preofs = sext i32 %iv to i64
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%preadr = getelementptr i8, i8* %base, i64 %preofs
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store i8 0, i8* %preadr
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%postiv = add i32 %iv, 1
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%postofs = sext i32 %postiv to i64
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%postadr = getelementptr i8, i8* %base, i64 %postofs
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store i8 0, i8* %postadr
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%postivnsw = add nsw i32 %ivnsw, 1
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%postofsnsw = sext i32 %postivnsw to i64
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%postadrnsw = getelementptr i8, i8* %base, i64 %postofsnsw
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store i8 0, i8* %postadrnsw
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%cond = icmp sgt i32 %limit, %postiv
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br i1 %cond, label %loop, label %exit
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exit:
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br label %return
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return:
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ret void
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}
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; Test sign extend elimination in the inner and outer loop.
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; %outercount is straightforward to widen, besides being in an outer loop.
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; %innercount is currently blocked by lcssa, so is not widened.
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; %inneriv can be widened only after proving it has no signed-overflow
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; based on the loop test.
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define void @nestedIV(i8* %address, i32 %limit) nounwind {
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; CHECK-LABEL: @nestedIV(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LIMITDEC:%.*]] = add i32 [[LIMIT:%.*]], -1
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; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[LIMITDEC]] to i64
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; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[LIMIT]], i32 1)
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
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; CHECK-NEXT: br label [[OUTERLOOP:%.*]]
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; CHECK: outerloop:
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; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[OUTERMERGE:%.*]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[INNERCOUNT:%.*]] = phi i32 [ [[INNERCOUNT_MERGE:%.*]], [[OUTERMERGE]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
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; CHECK-NEXT: [[ADR1:%.*]] = getelementptr i8, i8* [[ADDRESS:%.*]], i64 [[TMP1]]
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; CHECK-NEXT: store i8 0, i8* [[ADR1]], align 1
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; CHECK-NEXT: br label [[INNERPREHEADER:%.*]]
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; CHECK: innerpreheader:
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; CHECK-NEXT: [[INNERPRECMP:%.*]] = icmp sgt i32 [[LIMITDEC]], [[INNERCOUNT]]
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; CHECK-NEXT: br i1 [[INNERPRECMP]], label [[INNERLOOP_PREHEADER:%.*]], label [[OUTERMERGE]]
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; CHECK: innerloop.preheader:
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; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[INNERCOUNT]] to i64
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; CHECK-NEXT: br label [[INNERLOOP:%.*]]
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; CHECK: innerloop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP2]], [[INNERLOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[INNERLOOP]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[ADR2:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store i8 0, i8* [[ADR2]], align 1
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; CHECK-NEXT: [[ADR3:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i8 0, i8* [[ADR3]], align 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label [[INNEREXIT:%.*]]
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; CHECK: innerexit:
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; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[INNERLOOP]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]] to i32
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; CHECK-NEXT: br label [[OUTERMERGE]]
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; CHECK: outermerge:
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; CHECK-NEXT: [[INNERCOUNT_MERGE]] = phi i32 [ [[TMP3]], [[INNEREXIT]] ], [ [[INNERCOUNT]], [[INNERPREHEADER]] ]
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; CHECK-NEXT: [[ADR4:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV1]]
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; CHECK-NEXT: store i8 0, i8* [[ADR4]], align 1
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; CHECK-NEXT: [[OFS5:%.*]] = sext i32 [[INNERCOUNT_MERGE]] to i64
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; CHECK-NEXT: [[ADR5:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[OFS5]]
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; CHECK-NEXT: store i8 0, i8* [[ADR5]], align 1
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; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
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; CHECK-NEXT: [[EXITCOND4:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT2]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br i1 [[EXITCOND4]], label [[OUTERLOOP]], label [[RETURN:%.*]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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entry:
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%limitdec = add i32 %limit, -1
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br label %outerloop
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; Eliminate %ofs1 after widening outercount.
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; IV rewriting hoists a gep into this block. We don't like that.
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outerloop:
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%outercount = phi i32 [ %outerpostcount, %outermerge ], [ 0, %entry ]
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%innercount = phi i32 [ %innercount.merge, %outermerge ], [ 0, %entry ]
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%outercountdec = add i32 %outercount, -1
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%ofs1 = sext i32 %outercountdec to i64
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%adr1 = getelementptr i8, i8* %address, i64 %ofs1
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store i8 0, i8* %adr1
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br label %innerpreheader
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innerpreheader:
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%innerprecmp = icmp sgt i32 %limitdec, %innercount
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br i1 %innerprecmp, label %innerloop, label %outermerge
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; Eliminate %ofs2 after widening inneriv.
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; Eliminate %ofs3 after normalizing sext(innerpostiv)
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; FIXME: We should check that indvars does not increase the number of
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; IVs in this loop. sext elimination plus LFTR currently results in 2 final
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; IVs. Waiting to remove LFTR.
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innerloop:
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%inneriv = phi i32 [ %innerpostiv, %innerloop ], [ %innercount, %innerpreheader ]
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%innerpostiv = add i32 %inneriv, 1
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%ofs2 = sext i32 %inneriv to i64
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%adr2 = getelementptr i8, i8* %address, i64 %ofs2
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store i8 0, i8* %adr2
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%ofs3 = sext i32 %innerpostiv to i64
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%adr3 = getelementptr i8, i8* %address, i64 %ofs3
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store i8 0, i8* %adr3
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%innercmp = icmp sgt i32 %limitdec, %innerpostiv
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br i1 %innercmp, label %innerloop, label %innerexit
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innerexit:
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%innercount.lcssa = phi i32 [ %innerpostiv, %innerloop ]
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br label %outermerge
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; Eliminate %ofs4 after widening outercount
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; TODO: Eliminate %ofs5 after removing lcssa
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outermerge:
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%innercount.merge = phi i32 [ %innercount.lcssa, %innerexit ], [ %innercount, %innerpreheader ]
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%ofs4 = sext i32 %outercount to i64
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%adr4 = getelementptr i8, i8* %address, i64 %ofs4
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store i8 0, i8* %adr4
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%ofs5 = sext i32 %innercount.merge to i64
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%adr5 = getelementptr i8, i8* %address, i64 %ofs5
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store i8 0, i8* %adr5
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%outerpostcount = add i32 %outercount, 1
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%tmp47 = icmp slt i32 %outerpostcount, %limit
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br i1 %tmp47, label %outerloop, label %return
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return:
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ret void
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}
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