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45f41f7ab1
This is a more general alternative/extension to D102635. Rather than handling the special case of "header exit with non-exiting latch", this unrolls against the smallest exact trip count from any exit. The latch exit is no longer treated as priviledged when it comes to full unrolling. The motivating case is in full-unroll-one-unpredictable-exit.ll. Here the header exit is an IV-based exit, while the latch exit is a data comparison. This kind of loop does not get rotated, because the latch is already exiting, and loop rotation doesn't try to distinguish IV-based/analyzable latches. Differential Revision: https://reviews.llvm.org/D102982
87 lines
3.8 KiB
LLVM
87 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-unroll -S %s | FileCheck %s
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; Loop with multiple exiting blocks, where the header exits but not the latch,
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; e.g. because it has not been rotated.
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define i16 @full_unroll_multiple_exiting_blocks(i16* %A, i16 %x, i16 %y) {
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; CHECK-LABEL: @full_unroll_multiple_exiting_blocks(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[LV:%.*]] = load i16, i16* [[A:%.*]], align 2
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; CHECK-NEXT: [[RES_NEXT:%.*]] = add i16 123, [[LV]]
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; CHECK-NEXT: br label [[EXITING_1:%.*]]
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; CHECK: exiting.1:
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; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i16 [[LV]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[EC_1]], label [[EXIT:%.*]], label [[EXITING_2:%.*]]
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; CHECK: exiting.2:
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; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i16 [[LV]], [[Y:%.*]]
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; CHECK-NEXT: br i1 [[EC_2]], label [[EXIT]], label [[LATCH:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 1
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; CHECK-NEXT: [[LV_1:%.*]] = load i16, i16* [[PTR_1]], align 2
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; CHECK-NEXT: [[RES_NEXT_1:%.*]] = add i16 [[RES_NEXT]], [[LV_1]]
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; CHECK-NEXT: br label [[EXITING_1_1:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i16 [ 0, [[EXITING_1]] ], [ 1, [[EXITING_2]] ], [ 0, [[EXITING_1_1]] ], [ 1, [[EXITING_2_1:%.*]] ], [ 0, [[EXITING_1_2:%.*]] ], [ 1, [[EXITING_2_2:%.*]] ], [ [[RES_NEXT_3:%.*]], [[LATCH_2:%.*]] ], [ 0, [[EXITING_1_3:%.*]] ], [ 1, [[EXITING_2_3:%.*]] ]
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; CHECK-NEXT: ret i16 [[RES_LCSSA]]
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; CHECK: exiting.1.1:
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; CHECK-NEXT: [[EC_1_1:%.*]] = icmp eq i16 [[LV_1]], [[X]]
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; CHECK-NEXT: br i1 [[EC_1_1]], label [[EXIT]], label [[EXITING_2_1]]
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; CHECK: exiting.2.1:
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; CHECK-NEXT: [[EC_2_1:%.*]] = icmp eq i16 [[LV_1]], [[Y]]
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; CHECK-NEXT: br i1 [[EC_2_1]], label [[EXIT]], label [[LATCH_1:%.*]]
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; CHECK: latch.1:
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; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 2
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; CHECK-NEXT: [[LV_2:%.*]] = load i16, i16* [[PTR_2]], align 2
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; CHECK-NEXT: [[RES_NEXT_2:%.*]] = add i16 [[RES_NEXT_1]], [[LV_2]]
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; CHECK-NEXT: br label [[EXITING_1_2]]
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; CHECK: exiting.1.2:
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; CHECK-NEXT: [[EC_1_2:%.*]] = icmp eq i16 [[LV_2]], [[X]]
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; CHECK-NEXT: br i1 [[EC_1_2]], label [[EXIT]], label [[EXITING_2_2]]
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; CHECK: exiting.2.2:
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; CHECK-NEXT: [[EC_2_2:%.*]] = icmp eq i16 [[LV_2]], [[Y]]
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; CHECK-NEXT: br i1 [[EC_2_2]], label [[EXIT]], label [[LATCH_2]]
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; CHECK: latch.2:
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; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 3
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; CHECK-NEXT: [[LV_3:%.*]] = load i16, i16* [[PTR_3]], align 2
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; CHECK-NEXT: [[RES_NEXT_3]] = add i16 [[RES_NEXT_2]], [[LV_3]]
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; CHECK-NEXT: br i1 false, label [[EXITING_1_3]], label [[EXIT]]
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; CHECK: exiting.1.3:
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; CHECK-NEXT: [[EC_1_3:%.*]] = icmp eq i16 [[LV_3]], [[X]]
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; CHECK-NEXT: br i1 [[EC_1_3]], label [[EXIT]], label [[EXITING_2_3]]
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; CHECK: exiting.2.3:
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; CHECK-NEXT: [[EC_2_3:%.*]] = icmp eq i16 [[LV_3]], [[Y]]
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; CHECK-NEXT: br i1 [[EC_2_3]], label [[EXIT]], label [[LATCH_3:%.*]]
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; CHECK: latch.3:
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; CHECK-NEXT: unreachable
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;
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entry:
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br label %header
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header:
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%res = phi i16 [ 123, %entry ], [ %res.next, %latch ]
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%i.0 = phi i64 [ 0, %entry ], [ %inc9, %latch ]
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%ptr = getelementptr inbounds i16, i16* %A, i64 %i.0
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%lv = load i16, i16* %ptr
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%res.next = add i16 %res, %lv
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%cmp = icmp ult i64 %i.0, 3
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br i1 %cmp, label %exiting.1, label %exit
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exiting.1:
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%ec.1 = icmp eq i16 %lv, %x
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br i1 %ec.1, label %exit, label %exiting.2
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exiting.2:
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%ec.2 = icmp eq i16 %lv, %y
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br i1 %ec.2, label %exit, label %latch
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latch:
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%inc9 = add i64 %i.0, 1
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br label %header
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exit:
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%res.lcssa = phi i16 [ %res.next, %header ], [ 0, %exiting.1 ], [ 1, %exiting.2 ]
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ret i16 %res.lcssa
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}
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