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52 lines
1.9 KiB
C++
52 lines
1.9 KiB
C++
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "X86GenInstrInfo.inc"
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X86InstrInfo::X86InstrInfo()
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: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
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}
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// createNOPinstr - returns the target's implementation of NOP, which is
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// usually a pseudo-instruction, implemented by a degenerate version of
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// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
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//
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MachineInstr* X86InstrInfo::createNOPinstr() const {
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return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
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.addReg(X86::AX, MOTy::UseAndDef);
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}
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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//
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bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `xchg ax, ax'
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if (MI.getOpcode() == X86::XCHGrr16) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
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op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX) {
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return true;
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}
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}
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// FIXME: there are several NOOP instructions, we should check for them here.
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return false;
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}
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