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The DWARF specification knows 3 kinds of non-empty simple location descriptions: 1. Register location descriptions - describe a variable in a register - consist of only a DW_OP_reg 2. Memory location descriptions - describe the address of a variable 3. Implicit location descriptions - describe the value of a variable - end with DW_OP_stack_value & friends The existing DwarfExpression code is pretty much ignorant of these restrictions. This used to not matter because we only emitted very short expressions that we happened to get right by accident. This patch makes DwarfExpression aware of the rules defined by the DWARF standard and now chooses the right kind of location description for each expression being emitted. This would have been an NFC commit (for the existing testsuite) if not for the way that clang describes captured block variables. Based on how the previous code in LLVM emitted locations, DW_OP_deref operations that should have come at the end of the expression are put at its beginning. Fixing this means changing the semantics of DIExpression, so this patch bumps the version number of DIExpression and implements a bitcode upgrade. There are two major changes in this patch: I had to fix the semantics of dbg.declare for describing function arguments. After this patch a dbg.declare always takes the *address* of a variable as the first argument, even if the argument is not an alloca. When lowering a DBG_VALUE, the decision of whether to emit a register location description or a memory location description depends on the MachineLocation — register machine locations may get promoted to memory locations based on their DIExpression. (Future) optimization passes that want to salvage implicit debug location for variables may do so by appending a DW_OP_stack_value. For example: DBG_VALUE, [RBP-8] --> DW_OP_fbreg -8 DBG_VALUE, RAX --> DW_OP_reg0 +0 DBG_VALUE, RAX, DIExpression(DW_OP_deref) --> DW_OP_reg0 +0 All testcases that were modified were regenerated from clang. I also added source-based testcases for each of these to the debuginfo-tests repository over the last week to make sure that no synchronized bugs slip in. The debuginfo-tests compile from source and run the debugger. https://bugs.llvm.org/show_bug.cgi?id=32382 <rdar://problem/31205000> Differential Revision: https://reviews.llvm.org/D31439 llvm-svn: 300522
541 lines
21 KiB
C++
541 lines
21 KiB
C++
//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes a function named BuildMI, which is useful for dramatically
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// simplifying how MachineInstr's are created. It allows use of code like this:
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//
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// M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
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// .addReg(argVal1)
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// .addReg(argVal2);
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
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#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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#include <utility>
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namespace llvm {
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class MCInstrDesc;
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class MDNode;
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namespace RegState {
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enum {
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Define = 0x2,
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Implicit = 0x4,
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Kill = 0x8,
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Dead = 0x10,
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Undef = 0x20,
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EarlyClobber = 0x40,
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Debug = 0x80,
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InternalRead = 0x100,
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DefineNoRead = Define | Undef,
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ImplicitDefine = Implicit | Define,
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ImplicitKill = Implicit | Kill
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};
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} // end namespace RegState
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class MachineInstrBuilder {
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MachineFunction *MF = nullptr;
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MachineInstr *MI = nullptr;
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public:
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MachineInstrBuilder() = default;
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/// Create a MachineInstrBuilder for manipulating an existing instruction.
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/// F must be the machine function that was used to allocate I.
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MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
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MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
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: MF(&F), MI(&*I) {}
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/// Allow automatic conversion to the machine instruction we are working on.
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operator MachineInstr*() const { return MI; }
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MachineInstr *operator->() const { return MI; }
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operator MachineBasicBlock::iterator() const { return MI; }
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/// If conversion operators fail, use this method to get the MachineInstr
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/// explicitly.
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MachineInstr *getInstr() const { return MI; }
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/// Add a new virtual register operand.
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const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
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unsigned SubReg = 0) const {
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assert((flags & 0x1) == 0 &&
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"Passing in 'true' to addReg is forbidden! Use enums instead.");
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MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
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flags & RegState::Define,
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flags & RegState::Implicit,
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flags & RegState::Kill,
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flags & RegState::Dead,
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flags & RegState::Undef,
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flags & RegState::EarlyClobber,
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SubReg,
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flags & RegState::Debug,
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flags & RegState::InternalRead));
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return *this;
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}
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/// Add a virtual register definition operand.
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const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0,
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unsigned SubReg = 0) const {
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return addReg(RegNo, Flags | RegState::Define, SubReg);
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}
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/// Add a virtual register use operand. It is an error for Flags to contain
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/// `RegState::Define` when calling this function.
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const MachineInstrBuilder &addUse(unsigned RegNo, unsigned Flags = 0,
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unsigned SubReg = 0) const {
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assert(!(Flags & RegState::Define) &&
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"Misleading addUse defines register, use addReg instead.");
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return addReg(RegNo, Flags, SubReg);
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}
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/// Add a new immediate operand.
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const MachineInstrBuilder &addImm(int64_t Val) const {
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MI->addOperand(*MF, MachineOperand::CreateImm(Val));
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return *this;
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}
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const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
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MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
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return *this;
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}
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const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
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MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
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return *this;
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}
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const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addFrameIndex(int Idx) const {
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MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
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return *this;
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}
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const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
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int Offset = 0,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
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TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
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int64_t Offset = 0,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addExternalSymbol(const char *FnName,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
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int64_t Offset = 0,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
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MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
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return *this;
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}
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const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
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MI->addMemOperand(*MF, MMO);
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return *this;
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}
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const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b,
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MachineInstr::mmo_iterator e) const {
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MI->setMemRefs(b, e);
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return *this;
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}
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const MachineInstrBuilder &setMemRefs(std::pair<MachineInstr::mmo_iterator,
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unsigned> MemOperandsRef) const {
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MI->setMemRefs(MemOperandsRef);
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return *this;
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}
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const MachineInstrBuilder &add(const MachineOperand &MO) const {
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MI->addOperand(*MF, MO);
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return *this;
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}
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const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
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for (const MachineOperand &MO : MOs) {
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MI->addOperand(*MF, MO);
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}
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return *this;
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}
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const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
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MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
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assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
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: true) &&
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"first MDNode argument of a DBG_VALUE not a variable");
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return *this;
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}
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const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
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MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
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return *this;
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}
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const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
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MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
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return *this;
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}
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const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
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MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
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return *this;
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}
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const MachineInstrBuilder &addSym(MCSymbol *Sym,
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unsigned char TargetFlags = 0) const {
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MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
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return *this;
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}
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const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
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MI->setFlags(Flags);
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return *this;
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}
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const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
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MI->setFlag(Flag);
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return *this;
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}
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// Add a displacement from an existing MachineOperand with an added offset.
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const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
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unsigned char TargetFlags = 0) const {
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// If caller specifies new TargetFlags then use it, otherwise the
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// default behavior is to copy the target flags from the existing
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// MachineOperand. This means if the caller wants to clear the
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// target flags it needs to do so explicitly.
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if (0 == TargetFlags)
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TargetFlags = Disp.getTargetFlags();
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switch (Disp.getType()) {
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default:
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llvm_unreachable("Unhandled operand type in addDisp()");
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case MachineOperand::MO_Immediate:
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return addImm(Disp.getImm() + off);
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case MachineOperand::MO_ConstantPoolIndex:
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return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
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TargetFlags);
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case MachineOperand::MO_GlobalAddress:
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return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
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TargetFlags);
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}
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}
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/// Copy all the implicit operands from OtherMI onto this one.
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const MachineInstrBuilder &
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copyImplicitOps(const MachineInstr &OtherMI) const {
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MI->copyImplicitOps(*MF, OtherMI);
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return *this;
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}
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};
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/// Builder interface. Specify how to create the initial instruction itself.
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inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
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const MCInstrDesc &MCID) {
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return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
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}
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/// This version of the builder sets up the first operand as a
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/// destination virtual register.
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inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
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const MCInstrDesc &MCID, unsigned DestReg) {
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return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
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.addReg(DestReg, RegState::Define);
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}
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/// This version of the builder inserts the newly-built instruction before
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/// the given position in the given MachineBasicBlock, and sets up the first
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/// operand as a destination virtual register.
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, const MCInstrDesc &MCID,
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unsigned DestReg) {
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MachineFunction &MF = *BB.getParent();
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MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
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BB.insert(I, MI);
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return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
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}
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/// This version of the builder inserts the newly-built instruction before
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/// the given position in the given MachineBasicBlock, and sets up the first
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/// operand as a destination virtual register.
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///
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/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
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/// added to the same bundle.
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::instr_iterator I,
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const DebugLoc &DL, const MCInstrDesc &MCID,
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unsigned DestReg) {
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MachineFunction &MF = *BB.getParent();
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MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
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BB.insert(I, MI);
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return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
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}
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
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const DebugLoc &DL, const MCInstrDesc &MCID,
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unsigned DestReg) {
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// Calling the overload for instr_iterator is always correct. However, the
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// definition is not available in headers, so inline the check.
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if (I.isInsideBundle())
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return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
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return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
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}
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
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const DebugLoc &DL, const MCInstrDesc &MCID,
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unsigned DestReg) {
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return BuildMI(BB, *I, DL, MCID, DestReg);
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}
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/// This version of the builder inserts the newly-built instruction before the
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/// given position in the given MachineBasicBlock, and does NOT take a
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/// destination register.
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL,
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const MCInstrDesc &MCID) {
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MachineFunction &MF = *BB.getParent();
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MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
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BB.insert(I, MI);
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return MachineInstrBuilder(MF, MI);
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}
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::instr_iterator I,
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const DebugLoc &DL,
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const MCInstrDesc &MCID) {
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MachineFunction &MF = *BB.getParent();
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MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
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BB.insert(I, MI);
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return MachineInstrBuilder(MF, MI);
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}
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
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const DebugLoc &DL,
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const MCInstrDesc &MCID) {
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// Calling the overload for instr_iterator is always correct. However, the
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// definition is not available in headers, so inline the check.
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if (I.isInsideBundle())
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return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID);
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return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
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}
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
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const DebugLoc &DL,
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const MCInstrDesc &MCID) {
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return BuildMI(BB, *I, DL, MCID);
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}
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/// This version of the builder inserts the newly-built instruction at the end
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/// of the given MachineBasicBlock, and does NOT take a destination register.
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
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const MCInstrDesc &MCID) {
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return BuildMI(*BB, BB->end(), DL, MCID);
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}
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/// This version of the builder inserts the newly-built instruction at the
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/// end of the given MachineBasicBlock, and sets up the first operand as a
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/// destination virtual register.
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
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const MCInstrDesc &MCID, unsigned DestReg) {
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return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
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}
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/// This version of the builder builds a DBG_VALUE intrinsic
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/// for either a value in a register or a register-indirect+offset
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/// address. The convention is that a DBG_VALUE is indirect iff the
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/// second operand is an immediate.
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MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
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const MCInstrDesc &MCID, bool IsIndirect,
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unsigned Reg, unsigned Offset,
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const MDNode *Variable, const MDNode *Expr);
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/// This version of the builder builds a DBG_VALUE intrinsic
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/// for either a value in a register or a register-indirect+offset
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/// address and inserts it at position I.
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MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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const MCInstrDesc &MCID, bool IsIndirect,
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unsigned Reg, unsigned Offset,
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const MDNode *Variable, const MDNode *Expr);
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/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
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MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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const MachineInstr &Orig, int FrameIndex);
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inline unsigned getDefRegState(bool B) {
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return B ? RegState::Define : 0;
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}
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inline unsigned getImplRegState(bool B) {
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return B ? RegState::Implicit : 0;
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}
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inline unsigned getKillRegState(bool B) {
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return B ? RegState::Kill : 0;
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}
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inline unsigned getDeadRegState(bool B) {
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return B ? RegState::Dead : 0;
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}
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inline unsigned getUndefRegState(bool B) {
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return B ? RegState::Undef : 0;
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}
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inline unsigned getInternalReadRegState(bool B) {
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return B ? RegState::InternalRead : 0;
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}
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inline unsigned getDebugRegState(bool B) {
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return B ? RegState::Debug : 0;
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}
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/// Get all register state flags from machine operand \p RegOp.
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inline unsigned getRegState(const MachineOperand &RegOp) {
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assert(RegOp.isReg() && "Not a register operand");
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return getDefRegState(RegOp.isDef()) |
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getImplRegState(RegOp.isImplicit()) |
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getKillRegState(RegOp.isKill()) |
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getDeadRegState(RegOp.isDead()) |
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getUndefRegState(RegOp.isUndef()) |
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getInternalReadRegState(RegOp.isInternalRead()) |
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getDebugRegState(RegOp.isDebug());
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}
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/// Helper class for constructing bundles of MachineInstrs.
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///
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/// MIBundleBuilder can create a bundle from scratch by inserting new
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/// MachineInstrs one at a time, or it can create a bundle from a sequence of
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/// existing MachineInstrs in a basic block.
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class MIBundleBuilder {
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MachineBasicBlock &MBB;
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MachineBasicBlock::instr_iterator Begin;
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MachineBasicBlock::instr_iterator End;
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public:
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/// Create an MIBundleBuilder that inserts instructions into a new bundle in
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/// BB above the bundle or instruction at Pos.
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MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
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: MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
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/// Create a bundle from the sequence of instructions between B and E.
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MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
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MachineBasicBlock::iterator E)
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: MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
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assert(B != E && "No instructions to bundle");
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++B;
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while (B != E) {
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MachineInstr &MI = *B;
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++B;
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MI.bundleWithPred();
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}
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}
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/// Create an MIBundleBuilder representing an existing instruction or bundle
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/// that has MI as its head.
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explicit MIBundleBuilder(MachineInstr *MI)
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: MBB(*MI->getParent()), Begin(MI),
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End(getBundleEnd(MI->getIterator())) {}
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/// Return a reference to the basic block containing this bundle.
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MachineBasicBlock &getMBB() const { return MBB; }
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/// Return true if no instructions have been inserted in this bundle yet.
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/// Empty bundles aren't representable in a MachineBasicBlock.
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bool empty() const { return Begin == End; }
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/// Return an iterator to the first bundled instruction.
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MachineBasicBlock::instr_iterator begin() const { return Begin; }
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/// Return an iterator beyond the last bundled instruction.
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MachineBasicBlock::instr_iterator end() const { return End; }
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/// Insert MI into this bundle before I which must point to an instruction in
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/// the bundle, or end().
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MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
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MachineInstr *MI) {
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MBB.insert(I, MI);
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if (I == Begin) {
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if (!empty())
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MI->bundleWithSucc();
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Begin = MI->getIterator();
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return *this;
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}
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if (I == End) {
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MI->bundleWithPred();
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return *this;
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}
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// MI was inserted in the middle of the bundle, so its neighbors' flags are
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// already fine. Update MI's bundle flags manually.
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MI->setFlag(MachineInstr::BundledPred);
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MI->setFlag(MachineInstr::BundledSucc);
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return *this;
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}
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/// Insert MI into MBB by prepending it to the instructions in the bundle.
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/// MI will become the first instruction in the bundle.
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MIBundleBuilder &prepend(MachineInstr *MI) {
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return insert(begin(), MI);
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}
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/// Insert MI into MBB by appending it to the instructions in the bundle.
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/// MI will become the last instruction in the bundle.
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MIBundleBuilder &append(MachineInstr *MI) {
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return insert(end(), MI);
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}
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
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