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e86b7c773c
This patch allows targets to define multiple cost values for each register so that the cost model can be more flexible and better used during the register allocation as per the target requirements. For AMDGPU the VGPR allocation will be more efficient if the register cost can be associated dynamically based on the calling convention. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D86836
37 lines
1.1 KiB
TableGen
37 lines
1.1 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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// Checks the CostPerUse value for the registers.
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include "llvm/Target/Target.td"
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let Namespace = "MyTarget" in {
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foreach Index = 0-3 in {
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// Adds register cost value 1.
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let CostPerUse = [1] in {
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def S#Index : Register <"s"#Index>;
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}
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}
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// CostPerUse by default to 0.
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def D0 : Register<"d0">;
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def D1 : Register<"d1">;
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} // Namespace = "MyTarget"
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def SRegs : RegisterClass<"MyTarget", [i32], 32, (sequence "S%u", 0, 3)>;
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def DRegs : RegisterClass<"MyTarget", [i32], 32, (sequence "D%u", 0, 1)>;
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def MyTarget : Target;
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// CHECK: static const uint8_t CostPerUseTable[] = {
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// CHECK-NEXT: 0, 0, 0, 1, 1, 1, 1, };
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// CHECK: static const bool InAllocatableClassTable[] = {
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// CHECK-NEXT: false, true, true, true, true, true, true, };
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// CHECK: static const TargetRegisterInfoDesc MyTargetRegInfoDesc = { // Extra Descriptors
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// CHECK-NEXT: CostPerUseTable, 1, InAllocatableClassTable};
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// CHECK: TargetRegisterInfo(&MyTargetRegInfoDesc, RegisterClasses, RegisterClasses+2,
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