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acf8746c63
The selection process being split into separate passes, we need generic opcodes to translate the LLVM IR to target independent code. This patch adds an opcode for addition: G_ADD. Differential Revision: http://reviews.llvm.org/D15472 llvm-svn: 258333
613 lines
23 KiB
C++
613 lines
23 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wraps target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes abort on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenIntrinsics.h"
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#include "CodeGenSchedule.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<unsigned>
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AsmParserNum("asmparsernum", cl::init(0),
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cl::desc("Make -gen-asm-parser emit assembly parser #N"));
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType llvm::getValueType(Record *Rec) {
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return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
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}
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std::string llvm::getName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::iPTR: return "TLI.getPointerTy()";
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case MVT::iPTRAny: return "TLI.getPointerTy()";
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default: return getEnumName(T);
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}
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}
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std::string llvm::getEnumName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "MVT::Other";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::Any: return "MVT::Any";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::vAny: return "MVT::vAny";
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case MVT::f16: return "MVT::f16";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::x86mmx: return "MVT::x86mmx";
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case MVT::Glue: return "MVT::Glue";
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case MVT::isVoid: return "MVT::isVoid";
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case MVT::v2i1: return "MVT::v2i1";
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case MVT::v4i1: return "MVT::v4i1";
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case MVT::v8i1: return "MVT::v8i1";
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case MVT::v16i1: return "MVT::v16i1";
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case MVT::v32i1: return "MVT::v32i1";
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case MVT::v64i1: return "MVT::v64i1";
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case MVT::v512i1: return "MVT::v512i1";
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case MVT::v1024i1: return "MVT::v1024i1";
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case MVT::v1i8: return "MVT::v1i8";
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case MVT::v2i8: return "MVT::v2i8";
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case MVT::v4i8: return "MVT::v4i8";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v32i8: return "MVT::v32i8";
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case MVT::v64i8: return "MVT::v64i8";
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case MVT::v128i8: return "MVT::v128i8";
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case MVT::v256i8: return "MVT::v256i8";
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case MVT::v1i16: return "MVT::v1i16";
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case MVT::v2i16: return "MVT::v2i16";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v16i16: return "MVT::v16i16";
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case MVT::v32i16: return "MVT::v32i16";
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case MVT::v64i16: return "MVT::v64i16";
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case MVT::v128i16: return "MVT::v128i16";
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case MVT::v1i32: return "MVT::v1i32";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v8i32: return "MVT::v8i32";
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case MVT::v16i32: return "MVT::v16i32";
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case MVT::v32i32: return "MVT::v32i32";
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case MVT::v64i32: return "MVT::v64i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v4i64: return "MVT::v4i64";
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case MVT::v8i64: return "MVT::v8i64";
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case MVT::v16i64: return "MVT::v16i64";
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case MVT::v32i64: return "MVT::v32i64";
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case MVT::v1i128: return "MVT::v1i128";
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case MVT::v2f16: return "MVT::v2f16";
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case MVT::v4f16: return "MVT::v4f16";
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case MVT::v8f16: return "MVT::v8f16";
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case MVT::v1f32: return "MVT::v1f32";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v8f32: return "MVT::v8f32";
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case MVT::v16f32: return "MVT::v16f32";
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case MVT::v1f64: return "MVT::v1f64";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v4f64: return "MVT::v4f64";
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case MVT::v8f64: return "MVT::v8f64";
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case MVT::token: return "MVT::token";
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case MVT::Metadata: return "MVT::Metadata";
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case MVT::iPTR: return "MVT::iPTR";
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case MVT::iPTRAny: return "MVT::iPTRAny";
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case MVT::Untyped: return "MVT::Untyped";
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default: llvm_unreachable("ILLEGAL VALUE TYPE!");
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}
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}
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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///
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std::string llvm::getQualifiedName(const Record *R) {
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std::string Namespace;
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if (R->getValue("Namespace"))
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Namespace = R->getValueAsString("Namespace");
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if (Namespace.empty()) return R->getName();
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return Namespace + "::" + R->getName();
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget(RecordKeeper &records)
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: Records(records) {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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PrintFatalError("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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PrintFatalError("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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}
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CodeGenTarget::~CodeGenTarget() {
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}
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const std::string &CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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std::string CodeGenTarget::getInstNamespace() const {
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for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
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// Make sure not to pick up "TargetOpcode" by accidentally getting
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// the namespace off the PHI instruction or something.
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if (Inst->Namespace != "TargetOpcode")
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return Inst->Namespace;
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}
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return "";
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *CodeGenTarget::getAsmParser() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
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if (AsmParserNum >= LI.size())
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PrintFatalError("Target does not have an AsmParser #" +
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Twine(AsmParserNum) + "!");
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return LI[AsmParserNum];
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}
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/// getAsmParserVariant - Return the AssmblyParserVariant definition for
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/// this target.
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///
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Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
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std::vector<Record*> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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if (i >= LI.size())
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PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
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"!");
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return LI[i];
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}
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/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
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/// available for this target.
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///
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unsigned CodeGenTarget::getAsmParserVariantCount() const {
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std::vector<Record*> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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return LI.size();
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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PrintFatalError("Target does not have an AsmWriter #" +
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Twine(AsmWriterNum) + "!");
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return LI[AsmWriterNum];
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}
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CodeGenRegBank &CodeGenTarget::getRegBank() const {
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if (!RegBank)
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RegBank = llvm::make_unique<CodeGenRegBank>(Records);
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return *RegBank;
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}
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void CodeGenTarget::ReadRegAltNameIndices() const {
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RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
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std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
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}
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
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const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
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StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
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if (I == Regs.end())
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return nullptr;
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return I->second;
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}
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std::vector<MVT::SimpleValueType> CodeGenTarget::
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getRegisterVTs(Record *R) const {
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const CodeGenRegister *Reg = getRegBank().getReg(R);
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std::vector<MVT::SimpleValueType> Result;
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for (const auto &RC : getRegBank().getRegClasses()) {
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if (RC.contains(Reg)) {
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ArrayRef<MVT::SimpleValueType> InVTs = RC.getValueTypes();
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Result.insert(Result.end(), InVTs.begin(), InVTs.end());
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}
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}
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// Remove duplicates.
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array_pod_sort(Result.begin(), Result.end());
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Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
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return Result;
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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for (const auto &RC : getRegBank().getRegClasses())
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LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
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// Remove duplicates.
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array_pod_sort(LegalValueTypes.begin(), LegalValueTypes.end());
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LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
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LegalValueTypes.end()),
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LegalValueTypes.end());
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}
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CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
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if (!SchedModels)
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SchedModels = llvm::make_unique<CodeGenSchedModels>(Records, *this);
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return *SchedModels;
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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PrintFatalError("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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Instructions[Insts[i]] = llvm::make_unique<CodeGenInstruction>(Insts[i]);
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}
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static const CodeGenInstruction *
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GetInstByName(const char *Name,
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const DenseMap<const Record*,
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std::unique_ptr<CodeGenInstruction>> &Insts,
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RecordKeeper &Records) {
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const Record *Rec = Records.getDef(Name);
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const auto I = Insts.find(Rec);
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if (!Rec || I == Insts.end())
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PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
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return I->second.get();
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}
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/// \brief Return all of the instructions defined by the target, ordered by
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/// their enum value.
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void CodeGenTarget::ComputeInstrsByEnum() const {
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// The ordering here must match the ordering in TargetOpcodes.h.
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// FIXME: It would be nice to have the opcode directly extracted
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// to avoid potential errors. At the very, least a compile time
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// error would be appreciated if the order does not match.
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static const char *const FixedInstrs[] = {
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"PHI", "INLINEASM", "CFI_INSTRUCTION", "EH_LABEL",
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"GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
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"IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
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"REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
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"LIFETIME_END", "STACKMAP", "PATCHPOINT", "LOAD_STACK_GUARD",
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"STATEPOINT", "LOCAL_ESCAPE", "FAULTING_LOAD_OP",
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// Generic opcodes for GlobalISel start here.
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"G_ADD",
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nullptr};
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const auto &Insts = getInstructions();
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for (const char *const *p = FixedInstrs; *p; ++p) {
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const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
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assert(Instr && "Missing target independent instruction");
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assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
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InstrsByEnum.push_back(Instr);
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}
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unsigned EndOfPredefines = InstrsByEnum.size();
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for (const auto &I : Insts) {
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const CodeGenInstruction *CGI = I.second.get();
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if (CGI->Namespace != "TargetOpcode")
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InstrsByEnum.push_back(CGI);
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}
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assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
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// All of the instructions are now in random order based on the map iteration.
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// Sort them by name.
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std::sort(InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
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[](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
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return Rec1->TheDef->getName() < Rec2->TheDef->getName();
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});
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
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/// encodings, reverse the bit order of all instructions.
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void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
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if (!isLittleEndianEncoding())
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return;
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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for (Record *R : Insts) {
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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unsigned numBits = BI->getNumBits();
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SmallVector<Init *, 16> NewBits(numBits);
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for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
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unsigned bitSwapIdx = numBits - bit - 1;
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Init *OrigBit = BI->getBit(bit);
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Init *BitSwap = BI->getBit(bitSwapIdx);
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NewBits[bit] = BitSwap;
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NewBits[bitSwapIdx] = OrigBit;
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}
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if (numBits % 2) {
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unsigned middle = (numBits + 1) / 2;
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NewBits[middle] = BI->getBit(middle);
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}
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BitsInit *NewBI = BitsInit::get(NewBits);
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// Update the bits in reversed order so that emitInstrOpBits will get the
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// correct endianness.
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R->getValue("Inst")->setValue(NewBI);
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}
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}
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/// guessInstructionProperties - Return true if it's OK to guess instruction
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/// properties instead of raising an error.
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///
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/// This is configurable as a temporary migration aid. It will eventually be
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/// permanently false.
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bool CodeGenTarget::guessInstructionProperties() const {
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return getInstructionSet()->getValueAsBit("guessInstructionProperties");
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}
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//===----------------------------------------------------------------------===//
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// ComplexPattern implementation
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//
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ComplexPattern::ComplexPattern(Record *R) {
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Ty = ::getValueType(R->getValueAsDef("Ty"));
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NumOperands = R->getValueAsInt("NumOperands");
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SelectFunc = R->getValueAsString("SelectFunc");
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RootNodes = R->getValueAsListOfDefs("RootNodes");
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// Parse the properties.
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Properties = 0;
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std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
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for (unsigned i = 0, e = PropList.size(); i != e; ++i)
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if (PropList[i]->getName() == "SDNPHasChain") {
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Properties |= 1 << SDNPHasChain;
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} else if (PropList[i]->getName() == "SDNPOptInGlue") {
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Properties |= 1 << SDNPOptInGlue;
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} else if (PropList[i]->getName() == "SDNPMayStore") {
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Properties |= 1 << SDNPMayStore;
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} else if (PropList[i]->getName() == "SDNPMayLoad") {
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Properties |= 1 << SDNPMayLoad;
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} else if (PropList[i]->getName() == "SDNPSideEffect") {
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Properties |= 1 << SDNPSideEffect;
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} else if (PropList[i]->getName() == "SDNPMemOperand") {
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Properties |= 1 << SDNPMemOperand;
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} else if (PropList[i]->getName() == "SDNPVariadic") {
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Properties |= 1 << SDNPVariadic;
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} else if (PropList[i]->getName() == "SDNPWantRoot") {
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Properties |= 1 << SDNPWantRoot;
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} else if (PropList[i]->getName() == "SDNPWantParent") {
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Properties |= 1 << SDNPWantParent;
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} else {
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PrintFatalError("Unsupported SD Node property '" +
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PropList[i]->getName() + "' on ComplexPattern '" +
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R->getName() + "'!");
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}
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}
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//===----------------------------------------------------------------------===//
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// CodeGenIntrinsic Implementation
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//===----------------------------------------------------------------------===//
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std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
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bool TargetOnly) {
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std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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std::vector<CodeGenIntrinsic> Result;
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for (unsigned i = 0, e = I.size(); i != e; ++i) {
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bool isTarget = I[i]->getValueAsBit("isTarget");
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if (isTarget == TargetOnly)
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Result.push_back(CodeGenIntrinsic(I[i]));
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}
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return Result;
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}
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CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
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TheDef = R;
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std::string DefName = R->getName();
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ModRef = ReadWriteMem;
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isOverloaded = false;
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isCommutative = false;
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canThrow = false;
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isNoReturn = false;
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isNoDuplicate = false;
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isConvergent = false;
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if (DefName.size() <= 4 ||
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std::string(DefName.begin(), DefName.begin() + 4) != "int_")
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PrintFatalError("Intrinsic '" + DefName + "' does not start with 'int_'!");
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EnumName = std::string(DefName.begin()+4, DefName.end());
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if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
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GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
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if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
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MSBuiltinName = R->getValueAsString("MSBuiltinName");
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TargetPrefix = R->getValueAsString("TargetPrefix");
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Name = R->getValueAsString("LLVMName");
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if (Name == "") {
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// If an explicit name isn't specified, derive one from the DefName.
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Name = "llvm.";
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for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
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Name += (EnumName[i] == '_') ? '.' : EnumName[i];
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} else {
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// Verify it starts with "llvm.".
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if (Name.size() <= 5 ||
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std::string(Name.begin(), Name.begin() + 5) != "llvm.")
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PrintFatalError("Intrinsic '" + DefName + "'s name does not start with 'llvm.'!");
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}
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// If TargetPrefix is specified, make sure that Name starts with
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// "llvm.<targetprefix>.".
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if (!TargetPrefix.empty()) {
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if (Name.size() < 6+TargetPrefix.size() ||
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std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
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!= (TargetPrefix + "."))
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PrintFatalError("Intrinsic '" + DefName + "' does not start with 'llvm." +
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TargetPrefix + ".'!");
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}
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// Parse the list of return types.
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std::vector<MVT::SimpleValueType> OverloadedVTs;
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ListInit *TypeList = R->getValueAsListInit("RetTypes");
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for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
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Record *TyEl = TypeList->getElementAsRecord(i);
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assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
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MVT::SimpleValueType VT;
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if (TyEl->isSubClassOf("LLVMMatchType")) {
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unsigned MatchTy = TyEl->getValueAsInt("Number");
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assert(MatchTy < OverloadedVTs.size() &&
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"Invalid matching number!");
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VT = OverloadedVTs[MatchTy];
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// It only makes sense to use the extended and truncated vector element
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// variants with iAny types; otherwise, if the intrinsic is not
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// overloaded, all the types can be specified directly.
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assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
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!TyEl->isSubClassOf("LLVMTruncatedType")) ||
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VT == MVT::iAny || VT == MVT::vAny) &&
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"Expected iAny or vAny type");
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} else {
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VT = getValueType(TyEl->getValueAsDef("VT"));
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}
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if (MVT(VT).isOverloaded()) {
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OverloadedVTs.push_back(VT);
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isOverloaded = true;
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}
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// Reject invalid types.
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if (VT == MVT::isVoid)
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PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
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IS.RetVTs.push_back(VT);
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IS.RetTypeDefs.push_back(TyEl);
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}
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// Parse the list of parameter types.
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TypeList = R->getValueAsListInit("ParamTypes");
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for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
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Record *TyEl = TypeList->getElementAsRecord(i);
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assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
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MVT::SimpleValueType VT;
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if (TyEl->isSubClassOf("LLVMMatchType")) {
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unsigned MatchTy = TyEl->getValueAsInt("Number");
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assert(MatchTy < OverloadedVTs.size() &&
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"Invalid matching number!");
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VT = OverloadedVTs[MatchTy];
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// It only makes sense to use the extended and truncated vector element
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// variants with iAny types; otherwise, if the intrinsic is not
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// overloaded, all the types can be specified directly.
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assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
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!TyEl->isSubClassOf("LLVMTruncatedType") &&
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!TyEl->isSubClassOf("LLVMVectorSameWidth") &&
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!TyEl->isSubClassOf("LLVMPointerToElt")) ||
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VT == MVT::iAny || VT == MVT::vAny) &&
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"Expected iAny or vAny type");
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} else
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VT = getValueType(TyEl->getValueAsDef("VT"));
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if (MVT(VT).isOverloaded()) {
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OverloadedVTs.push_back(VT);
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isOverloaded = true;
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}
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// Reject invalid types.
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if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
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PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
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IS.ParamVTs.push_back(VT);
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IS.ParamTypeDefs.push_back(TyEl);
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}
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// Parse the intrinsic properties.
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ListInit *PropList = R->getValueAsListInit("Properties");
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for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
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Record *Property = PropList->getElementAsRecord(i);
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assert(Property->isSubClassOf("IntrinsicProperty") &&
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"Expected a property!");
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if (Property->getName() == "IntrNoMem")
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ModRef = NoMem;
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else if (Property->getName() == "IntrReadArgMem")
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ModRef = ReadArgMem;
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else if (Property->getName() == "IntrReadMem")
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ModRef = ReadMem;
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else if (Property->getName() == "IntrReadWriteArgMem")
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ModRef = ReadWriteArgMem;
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else if (Property->getName() == "Commutative")
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isCommutative = true;
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else if (Property->getName() == "Throws")
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canThrow = true;
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else if (Property->getName() == "IntrNoDuplicate")
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isNoDuplicate = true;
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else if (Property->getName() == "IntrConvergent")
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isConvergent = true;
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else if (Property->getName() == "IntrNoReturn")
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isNoReturn = true;
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else if (Property->isSubClassOf("NoCapture")) {
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unsigned ArgNo = Property->getValueAsInt("ArgNo");
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ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
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} else if (Property->isSubClassOf("ReadOnly")) {
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unsigned ArgNo = Property->getValueAsInt("ArgNo");
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ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
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} else if (Property->isSubClassOf("ReadNone")) {
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unsigned ArgNo = Property->getValueAsInt("ArgNo");
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ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
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} else
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llvm_unreachable("Unknown property!");
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}
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// Sort the argument attributes for later benefit.
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std::sort(ArgumentAttributes.begin(), ArgumentAttributes.end());
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}
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