Sjoerd Meijer d7dd48669c RAS extensions are part of ARMv8.2-A. This change enables them by introducing a ... new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670		2016-06-03 14:03:27 +00:00
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AArch64	RAS extensions are part of ARMv8.2-A. This change enables them by introducing a	2016-06-03 14:03:27 +00:00
AMDGPU	[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.	2016-05-24 12:05:16 +00:00
ARM	RAS extensions are part of ARMv8.2-A. This change enables them by introducing a	2016-06-03 14:03:27 +00:00
Hexagon	[Hexagon] Treat all conditional branches as predicted (not-taken by default)	2016-05-09 18:22:07 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[MIPS][LLVM-MC] Fix Disassemble of Negative Offset	2016-05-24 09:57:10 +00:00
PowerPC	This reverts commit r265505.	2016-04-28 20:00:42 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Support LRVH and STRVH opcodes	2016-05-16 20:32:22 +00:00
X86	Add new flag and intrinsic support for MWAITX and MONITORX instructions	2016-05-18 11:59:12 +00:00
XCore