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6655b5e078
Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068
44 lines
1.6 KiB
LLVM
44 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple mipsel--linux-android -mattr=+dsp -verify-machineinstrs | FileCheck %s
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; Function below generates a v2i16 to f32 bitcast.
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; Test that we are able to match it.
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define float @f(<8 x i16>* %a) {
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; CHECK-LABEL: f:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addiu $sp, $sp, -32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
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; CHECK-NEXT: .cfi_offset 30, -4
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; CHECK-NEXT: move $fp, $sp
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; CHECK-NEXT: .cfi_def_cfa_register 30
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; CHECK-NEXT: addiu $1, $zero, -16
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; CHECK-NEXT: and $sp, $sp, $1
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; CHECK-NEXT: lw $1, 12($4)
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; CHECK-NEXT: lw $2, 0($4)
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; CHECK-NEXT: lw $3, 8($4)
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; CHECK-NEXT: sw $3, 8($sp)
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; CHECK-NEXT: sw $1, 12($sp)
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; CHECK-NEXT: sw $2, 0($sp)
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; CHECK-NEXT: lw $1, 4($4)
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; CHECK-NEXT: sw $1, 4($sp)
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; CHECK-NEXT: mtc1 $2, $f0
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; CHECK-NEXT: move $sp, $fp
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; CHECK-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: addiu $sp, $sp, 32
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entry:
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%m = alloca <8 x i16>
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%0 = load <8 x i16>, <8 x i16>* %a
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store <8 x i16> %0, <8 x i16>* %m
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%1 = bitcast <8 x i16> %0 to <4 x float>
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%2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%3 = shufflevector <8 x float> zeroinitializer, <8 x float> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
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%4 = bitcast <8 x float> %3 to <8 x i32>
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%5 = extractelement <8 x i32> %4, i32 0
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%6 = bitcast i32 %5 to float
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ret float %6
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}
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