Daniel Sanders 2a30e4fcab [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. ... Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018		2014-06-16 13:13:03 +00:00
..
invalid-mips4.s	[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6	2014-06-12 15:00:17 +00:00
invalid-mips5-wrong-error.s	[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them	2014-05-12 12:52:44 +00:00
invalid-mips5.s	[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6	2014-06-12 15:00:17 +00:00
valid.s	[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.	2014-06-16 13:13:03 +00:00