Daniel Sanders 2a30e4fcab [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. ... Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018		2014-06-16 13:13:03 +00:00
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invalid-mips64r2-xfail.s	[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them	2014-05-13 11:45:36 +00:00
invalid-mips64r2.s	[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2	2014-05-14 15:35:03 +00:00
valid-xfail.s	[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS.	2014-05-08 15:17:29 +00:00
valid.s	[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.	2014-06-16 13:13:03 +00:00