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e236141513
Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
63 lines
1.5 KiB
C++
63 lines
1.5 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#include "AMDGPU.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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namespace llvm {
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class GCNSubtarget;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class AMDGPUInstrInfo {
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public:
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explicit AMDGPUInstrInfo(const GCNSubtarget &st);
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static bool isUniformMMO(const MachineMemOperand *MMO);
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};
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namespace AMDGPU {
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struct RsrcIntrinsic {
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unsigned Intr;
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uint8_t RsrcArg;
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bool IsImage;
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};
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const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
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struct D16ImageDimIntrinsic {
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unsigned Intr;
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unsigned D16HelperIntr;
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};
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const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
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struct ImageDimIntrinsicInfo {
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unsigned Intr;
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unsigned BaseOpcode;
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MIMGDim Dim;
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};
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const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
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} // end AMDGPU namespace
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} // End llvm namespace
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#endif
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