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e236141513
Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
42 lines
1.2 KiB
C++
42 lines
1.2 KiB
C++
//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// TargetRegisterInfo interface that is implemented by all hw codegen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
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#define GET_REGINFO_HEADER
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#include "AMDGPUGenRegisterInfo.inc"
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namespace llvm {
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class GCNSubtarget;
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class TargetInstrInfo;
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struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
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AMDGPURegisterInfo();
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bool enableMultipleCopyHints() const override { return true; }
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/// \returns the sub reg enum value for the given \p Channel
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/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
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static unsigned getSubRegFromChannel(unsigned Channel);
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void reserveRegisterTuples(BitVector &, unsigned Reg) const;
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};
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} // End namespace llvm
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#endif
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