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838b988f86
Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
102 lines
2.7 KiB
C++
102 lines
2.7 KiB
C++
//===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for Mips.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "MipsRegisterBankInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#define GET_TARGET_REGBANK_IMPL
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#define DEBUG_TYPE "registerbankinfo"
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#include "MipsGenRegisterBank.inc"
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namespace llvm {
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namespace Mips {
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enum PartialMappingIdx {
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PMI_GPR,
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PMI_Min = PMI_GPR,
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};
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RegisterBankInfo::PartialMapping PartMappings[]{
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{0, 32, GPRBRegBank}
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};
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enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 };
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RegisterBankInfo::ValueMapping ValueMappings[] = {
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// invalid
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{nullptr, 0},
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// 3 operands in GPRs
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{&PartMappings[PMI_GPR - PMI_Min], 1},
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{&PartMappings[PMI_GPR - PMI_Min], 1},
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{&PartMappings[PMI_GPR - PMI_Min], 1}};
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} // end namespace Mips
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} // end namespace llvm
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using namespace llvm;
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MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
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: MipsGenRegisterBankInfo() {}
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const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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using namespace Mips;
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switch (RC.getID()) {
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case Mips::GPR32RegClassID:
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case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
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case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
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case Mips::SP32RegClassID:
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return getRegBank(Mips::GPRBRegBankID);
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default:
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llvm_unreachable("Register class not supported");
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}
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}
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const RegisterBankInfo::InstructionMapping &
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MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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unsigned Opc = MI.getOpcode();
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const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
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if (Mapping.isValid())
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return Mapping;
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using namespace TargetOpcode;
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unsigned NumOperands = MI.getNumOperands();
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const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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switch (Opc) {
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case G_ADD:
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case G_LOAD:
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case G_STORE:
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case G_GEP:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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break;
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case G_CONSTANT:
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case G_FRAME_INDEX:
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case G_GLOBAL_VALUE:
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OperandsMapping =
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getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
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break;
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default:
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return getInvalidInstructionMapping();
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}
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return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
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NumOperands);
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}
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