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874523adc5
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
62 lines
1.8 KiB
LLVM
62 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s -check-prefix=STATIC-O32
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; RUN: llc < %s -march=mips -relocation-model=pic | FileCheck %s -check-prefix=PIC-O32
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; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=PIC-N64
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define i32 @main() nounwind readnone {
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entry:
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%x = alloca i32, align 4 ; <i32*> [#uses=2]
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store volatile i32 2, i32* %x, align 4
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%0 = load volatile i32* %x, align 4 ; <i32> [#uses=1]
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; STATIC-O32: lui $[[R0:[0-9]+]], %hi($JTI0_0)
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; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
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; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
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; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0)
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; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
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; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
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; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0)
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; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0)
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; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3
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switch i32 %0, label %bb4 [
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i32 0, label %bb5
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i32 1, label %bb1
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i32 2, label %bb2
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i32 3, label %bb3
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]
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bb1: ; preds = %entry
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ret i32 2
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; CHECK: STATIC-O32: $BB0_2
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bb2: ; preds = %entry
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ret i32 0
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bb3: ; preds = %entry
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ret i32 3
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bb4: ; preds = %entry
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ret i32 4
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bb5: ; preds = %entry
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ret i32 1
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}
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; STATIC-O32: .align 2
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; STATIC-O32: $JTI0_0:
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; PIC-O32: .align 2
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; PIC-O32: $JTI0_0:
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-N64: .align 3
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; PIC-N64: $JTI0_0:
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; PIC-N64: .gpdword
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; PIC-N64: .gpdword
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; PIC-N64: .gpdword
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; PIC-N64: .gpdword
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