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llvm-mirror/test/MC/X86/x86_64-sse4a.s
Benjamin Kramer 0c823ae0ed Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
2012-05-29 19:05:25 +00:00

26 lines
676 B
ArmAsm

# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
extrq $2, $3, %xmm0
# CHECK: extrq $2, $3, %xmm0
# CHECK: encoding: [0x66,0x0f,0x78,0xc0,0x03,0x02]
extrq %xmm1, %xmm0
# CHECK: extrq %xmm1, %xmm0
# CHECK: encoding: [0x66,0x0f,0x79,0xc1]
insertq $6, $5, %xmm1, %xmm0
# CHECK: insertq $6, $5, %xmm1, %xmm0
# CHECK: encoding: [0xf2,0x0f,0x78,0xc1,0x05,0x06]
insertq %xmm1, %xmm0
# CHECK: insertq %xmm1, %xmm0
# CHECK: encoding: [0xf2,0x0f,0x79,0xc1]
movntsd %xmm0, (%rdi)
# CHECK: movntsd %xmm0, (%rdi)
# CHECK: encoding: [0xf2,0x0f,0x2b,0x07]
movntss %xmm0, (%rdi)
# CHECK: movntss %xmm0, (%rdi)
# CHECK: encoding: [0xf3,0x0f,0x2b,0x07]