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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
67 lines
2.8 KiB
LLVM
67 lines
2.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.fabs.f32(float) nounwind readnone
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declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
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declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone
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; FUNC-LABEL: {{^}}clamp_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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; EG: MOV_SAT
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define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_fabs_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @clamp_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fabs, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_fneg_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @clamp_fneg_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%src.fneg = fsub float -0.0, %src
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_fneg_fabs_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @clamp_fneg_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
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%src.fneg.fabs = fsub float -0.0, %src.fabs
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_0_1_amdil_legacy_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
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%clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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