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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
32 lines
1.1 KiB
LLVM
32 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s
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; This works because promote allocas pass replaces these with LDS atomics.
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; Private atomics have no real use, but at least shouldn't crash on it.
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define void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind {
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entry:
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%tmp = alloca [2 x i32]
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%tmp1 = getelementptr [2 x i32]* %tmp, i32 0, i32 0
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%tmp2 = getelementptr [2 x i32]* %tmp, i32 0, i32 1
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store i32 0, i32* %tmp1
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store i32 1, i32* %tmp2
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%tmp3 = getelementptr [2 x i32]* %tmp, i32 0, i32 %in
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%tmp4 = atomicrmw add i32* %tmp3, i32 7 acq_rel
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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define void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind {
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entry:
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%tmp = alloca [2 x i32]
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%tmp1 = getelementptr [2 x i32]* %tmp, i32 0, i32 0
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%tmp2 = getelementptr [2 x i32]* %tmp, i32 0, i32 1
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store i32 0, i32* %tmp1
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store i32 1, i32* %tmp2
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%tmp3 = getelementptr [2 x i32]* %tmp, i32 0, i32 %in
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%tmp4 = cmpxchg i32* %tmp3, i32 0, i32 1 acq_rel monotonic
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%val = extractvalue { i32, i1 } %tmp4, 0
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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