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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
103 lines
2.7 KiB
LLVM
103 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
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@var_v2i8 = global <2 x i8> zeroinitializer
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@var_v4i8 = global <4 x i8> zeroinitializer
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@var_v2i16 = global <2 x i16> zeroinitializer
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@var_v4i16 = global <4 x i16> zeroinitializer
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@var_v2i32 = global <2 x i32> zeroinitializer
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@var_v4i32 = global <4 x i32> zeroinitializer
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@var_v2i64 = global <2 x i64> zeroinitializer
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define void @test_v2i8tov2i32() {
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; CHECK-LABEL: test_v2i8tov2i32:
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%i8val = load <2 x i8>, <2 x i8>* @var_v2i8
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%i32val = sext <2 x i8> %i8val to <2 x i32>
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store <2 x i32> %i32val, <2 x i32>* @var_v2i32
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; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
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; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
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; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
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ret void
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}
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define void @test_v2i8tov2i64() {
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; CHECK-LABEL: test_v2i8tov2i64:
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%i8val = load <2 x i8>, <2 x i8>* @var_v2i8
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%i64val = sext <2 x i8> %i8val to <2 x i64>
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store <2 x i64> %i64val, <2 x i64>* @var_v2i64
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; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16]
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; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
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; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
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; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}}
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; %i64val = sext <2 x i8> %i8val to <2 x i64>
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; store <2 x i64> %i64val, <2 x i64>* @var_v2i64
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ret void
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}
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define void @test_v4i8tov4i16() {
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; CHECK-LABEL: test_v4i8tov4i16:
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%i8val = load <4 x i8>, <4 x i8>* @var_v4i8
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%i16val = sext <4 x i8> %i8val to <4 x i16>
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store <4 x i16> %i16val, <4 x i16>* @var_v4i16
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; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
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; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
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; CHECK-NOT: vmovl.s16
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ret void
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; CHECK: bx lr
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}
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define void @test_v4i8tov4i32() {
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; CHECK-LABEL: test_v4i8tov4i32:
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%i8val = load <4 x i8>, <4 x i8>* @var_v4i8
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%i16val = sext <4 x i8> %i8val to <4 x i32>
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store <4 x i32> %i16val, <4 x i32>* @var_v4i32
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; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
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; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
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; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
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ret void
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}
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define void @test_v2i16tov2i32() {
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; CHECK-LABEL: test_v2i16tov2i32:
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%i16val = load <2 x i16>, <2 x i16>* @var_v2i16
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%i32val = sext <2 x i16> %i16val to <2 x i32>
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store <2 x i32> %i32val, <2 x i32>* @var_v2i32
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; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
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; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
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; CHECK-NOT: vmovl
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ret void
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; CHECK: bx lr
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}
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define void @test_v2i16tov2i64() {
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; CHECK-LABEL: test_v2i16tov2i64:
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%i16val = load <2 x i16>, <2 x i16>* @var_v2i16
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%i64val = sext <2 x i16> %i16val to <2 x i64>
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store <2 x i64> %i64val, <2 x i64>* @var_v2i64
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; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
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; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
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; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]]
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ret void
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}
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