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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
81 lines
3.3 KiB
LLVM
81 lines
3.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}scalar_to_vector_v2i32:
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; SI: buffer_load_dword [[VAL:v[0-9]+]],
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; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]]
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; SI: buffer_store_short [[RESULT]]
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; SI: buffer_store_short [[RESULT]]
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; SI: buffer_store_short [[RESULT]]
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; SI: buffer_store_short [[RESULT]]
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; SI: s_endpgm
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define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%tmp1 = load i32 addrspace(1)* %in, align 4
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%bc = bitcast i32 %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_to_vector_v2f32:
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; SI: buffer_load_dword [[VAL:v[0-9]+]],
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; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]]
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; SI: buffer_store_short [[RESULT]]
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; SI: buffer_store_short [[RESULT]]
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; SI: buffer_store_short [[RESULT]]
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; SI: buffer_store_short [[RESULT]]
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; SI: s_endpgm
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define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%tmp1 = load float addrspace(1)* %in, align 4
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%bc = bitcast float %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
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ret void
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}
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; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
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; to produce one, but for some reason never made it to selection.
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; define void @scalar_to_vector_test2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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; %tmp1 = load i32 addrspace(1)* %in, align 4
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; %bc = bitcast i32 %tmp1 to <4 x i8>
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; %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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; store <8 x i8> %tmp2, <8 x i8> addrspace(1)* %out, align 4
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; ret void
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; }
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; define void @scalar_to_vector_test3(<4 x i32> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <2 x i64> undef, i64 12345, i32 0
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; %newvec1 = insertelement <2 x i64> %newvec0, i64 undef, i32 1
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; %bc = bitcast <2 x i64> %newvec1 to <4 x i32>
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; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4>
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; store <4 x i32> %add, <4 x i32> addrspace(1)* %out, align 16
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; ret void
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; }
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; define void @scalar_to_vector_test4(<8 x i16> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <4 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <4 x i32> %newvec0 to <8 x i16>
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; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>
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; store <8 x i16> %add, <8 x i16> addrspace(1)* %out, align 16
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; ret void
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; }
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; define void @scalar_to_vector_test5(<4 x i16> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>
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; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>
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; store <4 x i16> %add, <4 x i16> addrspace(1)* %out, align 16
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; ret void
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; }
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; define void @scalar_to_vector_test6(<4 x i16> addrspace(1)* %out) nounwind {
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; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>
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; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>
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; store <4 x i16> %add, <4 x i16> addrspace(1)* %out, align 16
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; ret void
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; }
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