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https://github.com/RPCS3/llvm-mirror.git
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cfa2c4b845
Make the FP register callee saved. This is tricky because now the FP needs to be spilled in the prolog relative to the incoming SP register, rather than the frame register used throughout the rest of the function. I don't like how this bypassess the standard mechanism for CSR spills just to get the correct insert point. I may look for a better solution, since all CSR VGPRs may also need to have all lanes activated. Another option might be to make getFrameIndexReference change the base register if the frame index is a CSR, and then try to figure out the right insertion point in emitProlog. If there is a free VGPR lane available for SGPR spilling, try to use it for the FP. If that would require intrtoducing a new VGPR spill, try to use a free call clobbered SGPR. Only fallback to introducing a new VGPR spill as a last resort. This also doesn't attempt to handle SGPR spilling with scalar stores. llvm-svn: 365372
248 lines
8.3 KiB
LLVM
248 lines
8.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 0
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; MESA: kernarg_segment_byte_size = 16
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; HSA: s_load_dword s0, s[4:5], 0x0
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define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 48
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; MESA: kernarg_segment_byte_size = 16
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; HSA: s_load_dword s0, s[4:5], 0x0
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 112
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; MESA: kernarg_segment_byte_size = 128
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; HSA: s_load_dword s0, s[4:5], 0x1c
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define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 160
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; MESA: kernarg_segment_byte_size = 128
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; HSA: s_load_dword s0, s[4:5], 0x1c
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}func_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: v_mov_b32_e32 v0, s4
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; MESA: v_mov_b32_e32 v1, s5
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; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
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; HSA: v_mov_b32_e32 v0, s4
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; HSA: v_mov_b32_e32 v1, s5
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; HSA: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: v_mov_b32_e32 v0, s4
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; MESA: v_mov_b32_e32 v1, s5
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; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
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; HSA: v_mov_b32_e32 v0, s4
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; HSA: v_mov_b32_e32 v1, s5
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; HSA: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @opencl_func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 0
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; MESA: kernarg_segment_byte_size = 16
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; GCN-NOT: s[4:5]
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; GCN-NOT: s4
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; GCN-NOT: s5
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 48
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; MESA: kernarg_segment_byte_size = 16
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; GCN-NOT: s[4:5]
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; GCN-NOT: s4
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; GCN-NOT: s5
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; GCN: s_swappc_b64
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 112
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; MESA: kernarg_segment_byte_size = 128
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; HSA: s_add_u32 s4, s4, 0x70
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; MESA: s_add_u32 s4, s4, 0x70
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; GCN: s_addc_u32 s5, s5, 0{{$}}
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 160
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; MESA: kernarg_segment_byte_size = 128
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; GCN: s_add_u32 s4, s4, 0x70
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; GCN: s_addc_u32 s5, s5, 0{{$}}
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; GCN: s_swappc_b64
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func:
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; GCN-NOT: s4
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; GCN-NOT: s5
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; GCN-NOT: s[4:5]
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define void @func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func:
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; GCN-NOT: s4
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; GCN-NOT: s5
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; GCN-NOT: s[4:5]
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define void @opencl_func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA-DAG: v_mov_b32_e32 v0, s4
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; MESA-DAG: v_mov_b32_e32 v1, s5
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; MESA-DAG: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
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; MESA: v_mov_b32_e32 v0, s6
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; MESA: v_mov_b32_e32 v1, s7
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; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
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; HSA: v_mov_b32_e32 v0, s4
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; HSA: v_mov_b32_e32 v1, s5
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; HSA: flat_load_dword v0, v[0:1]
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; GCN: s_waitcnt vmcnt(0)
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define void @func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
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%load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA-DAG: v_mov_b32_e32 v0, s4
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; MESA-DAG: v_mov_b32_e32 v1, s5
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; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
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; MESA-DAG: v_mov_b32_e32 v0, s6
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; MESA-DAG: v_mov_b32_e32 v1, s7
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; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
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; HSA: v_mov_b32_e32 v0, s4
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; HSA: v_mov_b32_e32 v1, s5
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; HSA: flat_load_dword v0, v[0:1]
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; GCN: s_waitcnt vmcnt(0)
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define void @opencl_func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
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%load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func:
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; GCN: s_add_u32 s6, s4, 0x70
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; GCN: s_addc_u32 s7, s5, 0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 {
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call void @func_kernarg_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_no_struct_align_padding:
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; HSA: kernarg_segment_byte_size = 120
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; MESA: kernarg_segment_byte_size = 84
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; GCN: kernarg_segment_alignment = 6
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define amdgpu_kernel void @kernel_implicitarg_no_struct_align_padding(<16 x i32>, i32) #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
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declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
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attributes #0 = { nounwind noinline }
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attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="48" }
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attributes #2 = { nounwind readnone speculatable }
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