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b99d414631
Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212276
56 lines
1.7 KiB
LLVM
56 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7 -mattr=+db | FileCheck %s
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; CHECK-LABEL: test
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define void @test() {
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call void @llvm.arm.dmb(i32 3) ; CHECK: dmb osh
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call void @llvm.arm.dsb(i32 7) ; CHECK: dsb nsh
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call void @llvm.arm.isb(i32 15) ; CHECK: isb sy
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ret void
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}
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; Important point is that the compiler should not reorder memory access
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; instructions around DMB.
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; Failure to do so, two STRs will collapse into one STRD.
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; CHECK-LABEL: test_dmb_reordering
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define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) {
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store i32 %a, i32* %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
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call void @llvm.arm.dmb(i32 15) ; CHECK: dmb sy
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%d1 = getelementptr i32* %d, i32 1
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store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
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ret void
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}
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; Similarly for DSB.
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; CHECK-LABEL: test_dsb_reordering
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define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) {
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store i32 %a, i32* %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
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call void @llvm.arm.dsb(i32 15) ; CHECK: dsb sy
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%d1 = getelementptr i32* %d, i32 1
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store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
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ret void
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}
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; And ISB.
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; CHECK-LABEL: test_isb_reordering
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define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) {
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store i32 %a, i32* %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
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call void @llvm.arm.isb(i32 15) ; CHECK: isb sy
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%d1 = getelementptr i32* %d, i32 1
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store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
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ret void
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}
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declare void @llvm.arm.dmb(i32)
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declare void @llvm.arm.dsb(i32)
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declare void @llvm.arm.isb(i32)
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