Chad Rosier 2b85e24119 [AArch64] Falkor supports Rounding Double Multiply Add/Subtract instructions. ... Falkor only partially implements the ARMv8.1a extensions, so this patch refactors the support for the SQRDML[A|S]H instruction into a separate feature. Differential Revision: https://reviews.llvm.org/D28681 llvm-svn: 292142		2017-01-16 16:28:43 +00:00
..
AArch64	[AArch64] Falkor supports Rounding Double Multiply Add/Subtract instructions.	2017-01-16 16:28:43 +00:00
AMDGPU	[AMDGPU] Implement f16 fcopysign and fcopysign(f32, f64)	2017-01-13 19:49:25 +00:00
ARM	[SelectionDAG] Add support for BITREVERSE constant folding	2017-01-16 13:39:00 +00:00
AVR
BPF
Generic	Reverted: Track validity of pass results	2017-01-15 10:23:18 +00:00
Hexagon
Inputs
Lanai
Mips	Reverted: Track validity of pass results	2017-01-15 10:23:18 +00:00
MIR
MSP430
NVPTX	[NVPTX] Add fptosi tests to convert-fp.ll.	2017-01-15 16:55:54 +00:00
PowerPC	Revert "[PowerPC] Expand ISEL instruction into if-then-else sequence."	2017-01-16 15:01:07 +00:00
SPARC	Check for register clobbers when merging a vreg live range with a	2017-01-13 19:08:36 +00:00
SystemZ	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
Thumb	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
Thumb2	ARM: match GCC's behaviour for builtins	2017-01-13 16:25:33 +00:00
WebAssembly	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
WinEH
X86	[SelectionDAG] Add knownbits support for BITREVERSE	2017-01-16 14:49:26 +00:00
XCore