mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
92dfdbb7d5
On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. However, the default register class for 32-bit integers is GRX32, which also contains the high 32-bit part registers. In order to never end up with a case of such a COPY into a high reg, this patch adds a new simple pre-RA pass that selects such COPYs into target instructions. This pass also handles COPYs from CC (Condition Code register), and COPYs to CC can now also be emitted from a high reg in copyPhysReg(). Fixes: https://bugs.llvm.org/show_bug.cgi?id=44254 Review: Ulrich Weigand. Differential Revision: https://reviews.llvm.org/D75014
25 lines
746 B
LLVM
25 lines
746 B
LLVM
; RUN: llc < %s -mcpu=z196 -mtriple=s390x-linux-gnu -O0 \
|
|
; RUN: -stop-before=regallocfast 2>&1 | FileCheck %s
|
|
; RUN: llc < %s -mcpu=z196 -mtriple=s390x-linux-gnu -O3 \
|
|
; RUN: -stop-before=livevars 2>&1 | FileCheck %s
|
|
;
|
|
; Test that copies to/from access registers are handled before regalloc with
|
|
; GR32 regs.
|
|
|
|
@x = dso_local thread_local global i32 0, align 4
|
|
define weak_odr hidden i32* @fun0() {
|
|
; CHECK: name: fun0
|
|
; CHECK: {{%[0-9]+}}:gr32bit = EAR $a0
|
|
; CHECK: {{%[0-9]+}}:gr32bit = EAR $a1
|
|
ret i32* @x
|
|
}
|
|
|
|
define i32 @fun1() {
|
|
; CHECK: name: fun1
|
|
; CHECK: [[VREG0:%[0-9]+]]:gr32bit = COPY %0
|
|
; CHECK-NEXT: $a1 = SAR [[VREG0]]
|
|
; CHECK: {{%[0-9]+}}:gr32bit = EAR $a0
|
|
%val = call i32 asm "blah", "={a0}, {a1}" (i32 0)
|
|
ret i32 %val
|
|
}
|