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On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. However, the default register class for 32-bit integers is GRX32, which also contains the high 32-bit part registers. In order to never end up with a case of such a COPY into a high reg, this patch adds a new simple pre-RA pass that selects such COPYs into target instructions. This pass also handles COPYs from CC (Condition Code register), and COPYs to CC can now also be emitted from a high reg in copyPhysReg(). Fixes: https://bugs.llvm.org/show_bug.cgi?id=44254 Review: Ulrich Weigand. Differential Revision: https://reviews.llvm.org/D75014
38 lines
1.2 KiB
LLVM
38 lines
1.2 KiB
LLVM
; RUN: llc < %s -mcpu=z196 -mtriple=s390x-linux-gnu -O0
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;
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; Test that a0 and a1 are copied successfully into GR32 registers.
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@x = dso_local thread_local global i32 0, align 4
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define i32 @fun0(i32 signext, i32 signext, i32 signext, i32 signext, i32 signext, i32 signext, i32 signext) {
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%8 = alloca i32, align 4
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%9 = alloca i32, align 4
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%10 = alloca i32, align 4
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%11 = alloca i32, align 4
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%12 = alloca i32, align 4
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%13 = alloca i32, align 4
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%14 = alloca i32, align 4
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%15 = load i32, i32* @x, align 4
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store i32 %0, i32* %8, align 4
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store i32 %1, i32* %9, align 4
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store i32 %2, i32* %10, align 4
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store i32 %3, i32* %11, align 4
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store i32 %4, i32* %12, align 4
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store i32 %5, i32* %13, align 4
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store i32 %6, i32* %14, align 4
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%16 = load i32, i32* %8, align 4
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%17 = add nsw i32 %15, %16
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%18 = load i32, i32* %9, align 4
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%19 = add nsw i32 %17, %18
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%20 = load i32, i32* %10, align 4
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%21 = add nsw i32 %19, %20
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%22 = load i32, i32* %11, align 4
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%23 = add nsw i32 %21, %22
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%24 = load i32, i32* %12, align 4
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%25 = add nsw i32 %23, %24
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%26 = load i32, i32* %13, align 4
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%27 = add nsw i32 %25, %26
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%28 = load i32, i32* %14, align 4
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%29 = add nsw i32 %27, %28
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ret i32 %29
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}
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