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94738aa18e
have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
28 lines
1.6 KiB
LLVM
28 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
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; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
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; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
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; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
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; operand. There are many combinations that work; this is what llc puts out now.
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; ModuleID = '<stdin>'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin8"
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%struct.foo = type { i32, i32, i8* }
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define i32 @get(%struct.foo* %c, i8* %state) nounwind {
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entry:
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%0 = getelementptr %struct.foo* %c, i32 0, i32 0 ; <i32*> [#uses=2]
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%1 = getelementptr %struct.foo* %c, i32 0, i32 1 ; <i32*> [#uses=2]
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%2 = getelementptr %struct.foo* %c, i32 0, i32 2 ; <i8**> [#uses=2]
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%3 = load i32* %0, align 4 ; <i32> [#uses=1]
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%4 = load i32* %1, align 4 ; <i32> [#uses=1]
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%5 = load i8* %state, align 1 ; <i8> [#uses=1]
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%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
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%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
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%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
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store i32 %asmresult1, i32* %0
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%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
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store i32 %asmresult2, i32* %1
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ret i32 %asmresult
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}
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