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82ce325f16
reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
62 lines
1.6 KiB
LLVM
62 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; rdar://7527734
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define i32 @test1(i32 %x) nounwind readnone ssp {
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entry:
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; CHECK: test1:
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; CHECK: leal 3(%rdi), %eax
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%0 = shl i32 %x, 5 ; <i32> [#uses=1]
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%1 = or i32 %0, 3 ; <i32> [#uses=1]
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ret i32 %1
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}
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define i64 @test2(i8 %A, i8 %B) nounwind {
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; CHECK: test2:
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; CHECK: shrq $4
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; CHECK-NOT: movq
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; CHECK-NOT: orq
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; CHECK: leaq
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; CHECK: ret
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%C = zext i8 %A to i64 ; <i64> [#uses=1]
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%D = shl i64 %C, 4 ; <i64> [#uses=1]
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%E = and i64 %D, 48 ; <i64> [#uses=1]
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%F = zext i8 %B to i64 ; <i64> [#uses=1]
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%G = lshr i64 %F, 4 ; <i64> [#uses=1]
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%H = or i64 %G, %E ; <i64> [#uses=1]
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ret i64 %H
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}
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;; Test that OR is only emitted as LEA, not as ADD.
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define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
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entry:
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; No reason to emit an add here, should be an or.
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; CHECK: test3:
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; CHECK: orl $3, %edi
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%0 = shl i32 %x, 5
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%1 = or i32 %0, 3
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store i32 %1, i32* %P
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ret void
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}
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define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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%and = and i32 %a, 6
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%and2 = and i32 %b, 16
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%or = or i32 %and2, %and
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ret i32 %or
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; CHECK: test4:
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; CHECK: leal (%rsi,%rdi), %eax
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}
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define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp {
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entry:
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%and = and i32 %a, 6
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%and2 = and i32 %b, 16
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%or = or i32 %and2, %and
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store i32 %or, i32* %P, align 4
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ret void
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; CHECK: test5:
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; CHECK: orl
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}
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