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6e1367d5dd
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
llvm-svn: 128941
10 lines
618 B
Plaintext
10 lines
618 B
Plaintext
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
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# -------------------------------------------------------------------------------------------------
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# A8.6.89 LSL (register): Inst{7-4} = 0b0001
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0x93 0x42 0xa0 0xd1
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