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7e501cf4c3
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
llvm-svn: 186280
126 lines
4.5 KiB
LLVM
126 lines
4.5 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vpadals8:
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;CHECK: vpadal.s8
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vpadals16:
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;CHECK: vpadal.s16
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vpadals32:
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;CHECK: vpadal.s32
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vpadalu8:
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;CHECK: vpadal.u8
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vpadalu16:
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;CHECK: vpadal.u16
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vpadalu32:
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;CHECK: vpadal.u32
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vpadalQs8:
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;CHECK: vpadal.s8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vpadalQs16:
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;CHECK: vpadal.s16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vpadalQs32:
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;CHECK: vpadal.s32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vpadalQu8:
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;CHECK: vpadal.u8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vpadalQu16:
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;CHECK: vpadal.u16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vpadalQu32:
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;CHECK: vpadal.u32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
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