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b6a12c439f
This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
148 lines
3.3 KiB
LLVM
148 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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; If positive...
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define i32 @zext_ifpos(i32 %x) {
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; CHECK-LABEL: zext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: lsr w0, w8, #31
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_zext_ifpos(i32 %x) {
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; CHECK-LABEL: add_zext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: lsr w8, w8, #31
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; CHECK-NEXT: add w0, w8, #41 // =41
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define i32 @sel_ifpos_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_tval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, ge
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifpos(i32 %x) {
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; CHECK-LABEL: sext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: asr w0, w8, #31
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_sext_ifpos(i32 %x) {
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; CHECK-LABEL: add_sext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: mov w9, #42
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; CHECK-NEXT: sub w0, w9, w8, lsr #31
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define i32 @sel_ifpos_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_fval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, lt
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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; If negative...
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define i32 @zext_ifneg(i32 %x) {
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; CHECK-LABEL: zext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w0, w0, #31
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_zext_ifneg(i32 %x) {
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; CHECK-LABEL: add_zext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #41 // =41
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define i32 @sel_ifneg_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_tval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, lt
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifneg(i32 %x) {
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; CHECK-LABEL: sext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w0, w0, #31
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = sext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_sext_ifneg(i32 %x) {
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; CHECK-LABEL: add_sext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #42
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; CHECK-NEXT: sub w0, w8, w0, lsr #31
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define i32 @sel_ifneg_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_fval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, ge
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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