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559228e8d5
This adds an additional matcher to select UBFX(..) from SRL(AND(..)) in ARMISelDAGToDAG to help with code size. Patch by David Green. Differential Revision: http://reviews.llvm.org/D20667 llvm-svn: 271384
70 lines
1.7 KiB
LLVM
70 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s
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define i32 @sbfx1(i32 %a) {
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; CHECK: sbfx1
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; CHECK: sbfx r0, r0, #7, #11
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%t1 = lshr i32 %a, 7
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%t2 = trunc i32 %t1 to i11
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%t3 = sext i11 %t2 to i32
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ret i32 %t3
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}
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define i32 @ubfx1(i32 %a) {
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; CHECK: ubfx1
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; CHECK: ubfx r0, r0, #7, #11
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%t1 = lshr i32 %a, 7
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%t2 = trunc i32 %t1 to i11
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%t3 = zext i11 %t2 to i32
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ret i32 %t3
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}
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define i32 @ubfx2(i32 %a) {
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; CHECK: ubfx2
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; CHECK: ubfx r0, r0, #7, #11
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%t1 = lshr i32 %a, 7
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%t2 = and i32 %t1, 2047
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ret i32 %t2
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}
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; rdar://12870177
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define i32 @ubfx_opt(i32* nocapture %ctx, i32 %x) nounwind readonly ssp {
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entry:
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; CHECK: ubfx_opt
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; CHECK: lsr [[REG1:(lr|r[0-9]+)]], r1, #24
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; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG1]], lsl #2]
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; CHECK: ubfx [[REG2:(lr|r[0-9]+)]], r1, #16, #8
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; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG2]], lsl #2]
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; CHECK: ubfx [[REG3:(lr|r[0-9]+)]], r1, #8, #8
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; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG3]], lsl #2]
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%and = lshr i32 %x, 8
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%shr = and i32 %and, 255
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%and1 = lshr i32 %x, 16
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%shr2 = and i32 %and1, 255
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%shr4 = lshr i32 %x, 24
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%arrayidx = getelementptr inbounds i32, i32* %ctx, i32 %shr4
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%0 = load i32, i32* %arrayidx, align 4
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%arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2
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%1 = load i32, i32* %arrayidx5, align 4
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%add = add i32 %1, %0
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%arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr
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%2 = load i32, i32* %arrayidx6, align 4
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%add7 = add i32 %add, %2
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ret i32 %add7
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}
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define i32 @ubfx3(i32 %a) {
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; CHECK: ubfx3
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; CHECK: ubfx r0, r0, #11, #1
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%t1 = and i32 %a, 2048
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%t2 = lshr i32 %t1, 11
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ret i32 %t2
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}
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define i32 @ubfx4(i32 %a) {
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; CHECK: ubfx4
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; CHECK: ubfx r0, r0, #7, #3
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%t1 = and i32 %a, 896
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%t2 = lshr i32 %t1, 7
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ret i32 %t2
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}
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