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98866e3fe1
If we have an LDM that uses only low registers and doesn't write to its base register:
ldm.w r0, {r1, r2, r3}
And that base register is dead after the LDM, then we can convert it to writeback form and use a narrow encoding:
ldm.n r0!, {r1, r2, r3}
Obviously, this introduces a new register write and so can cause WAW hazards, so I've enabled it only in minsize mode. This is a code size trick that ARM Compiler 5 ("armcc") does that we don't.
llvm-svn: 272000
22 lines
648 B
LLVM
22 lines
648 B
LLVM
; RUN: llc -O3 < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "armv7--linux-gnu"
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@a = global i32 0, align 4
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@b = global i32 0, align 4
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@c = global i32 0, align 4
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; CHECK-LABEL: bar:
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; CHECK: ldm r{{[0-9]}}!, {r0, r{{[0-9]}}, r{{[0-9]}}}
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define void @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
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%1 = load i32, i32* @a, align 4
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%2 = load i32, i32* @b, align 4
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%3 = load i32, i32* @c, align 4
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%4 = tail call i32 @baz(i32 %1, i32 %3) minsize optsize
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%5 = tail call i32 @baz(i32 %2, i32 %3) minsize optsize
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ret void
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}
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declare i32 @baz(i32,i32) minsize optsize
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